Simulink Real-Time FPGA I/O 模块

在 Simulink^® Real-Time™ FPGA I/O 模块上生成和部署 HDL 代码（需要 Simulink Real-Time）

您可以生成 FPGA 编程文件和 Simulink Real-Time FPGA I/O 接口以在 Speedgoat^® I/O 模块上部署。请参阅IP Core Generation Workflow for Speedgoat Simulink-Programmable I/O Modules。

类

`hdlcoder.Board`	Board registration object that describes SoC custom board
`hdlcoder.WorkflowConfig`	Configure HDL code generation and deployment workflows
`hdlcoder.ReferenceDesign`	Reference design registration object that describes SoC reference design

socExportReferenceDesign Export custom reference design for HDL Workflow Advisor

`addExternalIOInterface`	Define external IO interface for board object
`addExternalPortInterface`	Define external port interface for board object
`addInternalIOInterface`	Add and define internal IO interface between generated IP core and existing IP cores
`addAXI4MasterInterface`	Add and define AXI4 Master interface
`addAXI4SlaveInterface`	Add and define AXI4 slave interface
`addAXI4StreamInterface`	Add AXI4-Stream interface
`addAXI4StreamVideoInterface`	Add AXI4-Stream Video interface
`addClockInterface`	Add clock and reset interface

`addCustomEDKDesign`	Specify Xilinx EDK MHS project file
`addCustomQsysDesign`	Specify Altera Qsys project file
`addCustomVivadoDesign`	Specify Xilinx Vivado exported block design Tcl file
`addIPRepository`	Include IP modules from your IP repository folder in your custom reference design
`addParameter`	Add and define custom parameters for your reference design
`validateReferenceDesign`	Check property values in reference design object
`validateBoard`	Check property values in board object

IP Core Generation Workflow for Speedgoat Simulink-Programmable I/O Modules
Use the IP Core Generation workflow with Speedgoat I/O modules and embed the IP core into the reference design.
Program Target FPGA Boards or SoC Devices
How to program the target Intel or Xilinx Hardware.
Generate Simulink Real-Time Interface Subsystem for Simscape Two-Level Converter Model
Generate HDL code and Simulink Real-Time interface model from Simscape™ models.
Speedgoat FPGA Support with HDL Workflow Advisor
Implementing Simulink algorithms on FPGAs on board Speedgoat FPGA I/O modules.
Map Bus Data Types to PCIe Interface
When you use bus data types at the DUT interface ports, you can directly map the interface ports to PCIe interfaces.

Resolve timing failures in Build FPGA Bitstream step of IP Core Generation Workflow or Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards.

Select and run HDL code generation and synthesis workflow for a Speedgoat target computer.

Deploy buck converter modeled in Simscape to Speedgoat IO modules using HDL Workflow script.

Synthesize and generate FPGA bitstream from a Simscape half-wave rectifier model and deploy it onto a Speedgoat FPGA I/O 334-325K target.