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addClockInterface

Class: hdlcoder.ReferenceDesign
Namespace: hdlcoder

Add clock and reset interface

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Syntax

addClockInterface('ClockConnection',clock_port,'ResetConnection',reset_port)
addClockInterface('ClockConnection',clock_port,'ResetConnection',reset_port,Name=Value)

Description

addClockInterface('ClockConnection',clock_port,'ResetConnection',reset_port) adds a clock and reset interface to an hdlcoder.ReferenceDesign object.

addClockInterface('ClockConnection',clock_port,'ResetConnection',reset_port,Name=Value) adds a clock and reset interface to the hdlcoder.ReferenceDesign object with additional options specified by one or more Name=Value arguments. When you specify these arguments, in the HDL Workflow Advisor, HDL Coder™ adds a Set Target Frequency task. To modify the output clock frequency setting in the reference design clock wizard, in this task, specify the Target Frequency (MHz).

The HDL Workflow Advisor adjusts the Set Target Frequency task in different ways, depending on how you specify these name-value arguments:

  • When DefaultFrequencyMHz, MinFrequencyMHz, and MaxFrequencyMHz are not specified or all set to zero, the HDL Workflow Advisor does not have the Set Target Frequency task.

  • When DefaultFrequencyMHz, MinFrequencyMHz, and MaxFrequencyMHz are all equal, the HDL Workflow Advisor adds the Set Target Frequency task, but the target frequency is not adjustable.

  • When MinFrequencyMHz is not equal to MaxFrequencyMHz, the HDL Workflow Advisor adds the Set Target Frequency task and the target frequency is adjustable. During the Create Project task, HDL Coder sets the target frequency on the specified clock module IP ClockModuleInstance and its specified clock output number ClockNumber in the reference design. If the ClockNumber and ClockModuleInstance arguments are not specified, the default values are used.

Input Arguments

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Reference design port that is connected to the IP core clock port, specified as a character vector.

Example: 'processing_system7_1/FCLK_CLK0'

Reference design port that is connected to the IP core reset port, specified as a character vector.

Example: 'proc_sys_reset/peripheral_aresetn'

Name-Value Arguments

Specify optional pairs of arguments as Name1=Value1,...,NameN=ValueN, where Name is the argument name and Value is the corresponding value. Name-value arguments must appear after other arguments, but the order of the pairs does not matter.

Before R2021a, use commas to separate each name and value, and enclose Name in quotes.

The default clock frequency in MHz of the clock module IP in the reference design, specified as an integer. When you open the HDL Workflow Advisor, HDL Coder populates this information for Default (MHz) in the Set Target Frequency task.

Example: 'DefaultFrequencyMHz',50 specifies the default frequency as 50 MHz.

The minimum clock frequency in MHz of the clock module IP in the reference design, specified as an integer.

Example: 'MinFrequencyMHz',5 specifies the minimum clock frequency as 5 MHz.

The maximum clock frequency in MHz of the clock module IP in the reference design, specified as an integer. In the HDL Workflow Advisor, HDL Coder sets the Frequency Range (MHz) in the Set Target Frequency task based on the MinFrequencyMHz and MaxFrequencyMHz values that you specify.

Example: 'MaxFrequencyMHz',500 specifies the maximum clock frequency as 500 MHz.

Port number of the clock output from the clock module IP in the reference design, specified as an integer. If you have a Vivado® reference design, use a one-based index to specify the clock port number. If you have a Quartus® reference design, use a zero-based index to specify the clock port number.

Example: 'ClockNumber',1 specifies the first output port in the clock module IP to use as the clock port for a Vivado reference design.

Example: 'ClockNumber',0 specifies the first output port in the clock module IP to use as the clock port for a Quartus reference design.

The name of the clock module IP in the reference design, specified as a character vector.

Example: 'ClockModuleInstance','clk_wiz_1' specifies clk_wiz_1 as the name of the clock module IP.

Version History

Introduced in R2015a

See Also

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