生成和部署 IP 核
R2026bIP 核是实现特定函数（通常是算法）的可移植和可重用的 HDL 组件。IP 核由以下各项组成：为您的算法生成的 HDL 代码、打包的 IP 核定义文件、包含寄存器地址映射的 C 头文件以及 IP 核报告。
使用 HDL Coder™，您可以从您的 MATLAB® 函数或 Simulink® 模型生成 IP 核。生成的 IP 核可以手动集成到现有系统中，也可以使用参考设计自动部署。有关手动集成生成的 IP 核的示例，请参阅Generate Board-Independent HDL IP Core for Xilinx Platforms。
要自动部署您的 IP 核，请使用参考设计，它定义生成的 IP 核如何集成到完整系统中。HDL Coder 为许多常见硬件平台和应用提供参考设计。您也可以编写自己的自定义参考设计。请参阅在自定义硬件上部署 IP 核。
如果您的硬件平台没有预先编写的参考设计，HDL Coder 可以自动为您生成一个参考设计。通过为您的参考设计选择自动生成，HDL Coder 会构建一个完整的、可部署的系统，其中包含您生成的 IP 核。有关详细信息，请参阅 Deploy IP Core With Auto-Generated Reference Design。
有关工作流的更多详细信息，请参阅Targeting FPGA and SoC Hardware Overview。
类
hdlcoder.WorkflowConfig | Configure HDL code generation and deployment workflows |
主题
IP 核生成
- Custom IP Core Generation
Generate a custom IP core from a model or algorithm using the HDL Workflow Advisor. - Custom IP Core Report
You generate an HTML custom IP core report by default when you generate a custom IP core. - Generate Board-Independent HDL IP Core from Simulink Model
When you open the HDL Workflow Advisor and run theIP Core Generationworkflow for your Simulink model, you can specify a generic Xilinx® platform, a generic Intel® platform, generic Microchip platform or generic platform. - Generate Board-Independent IP Core from MATLAB Algorithm
Board-independent IP core generation from MATLAB. - Generate HDL IP Core with Multiple AXI4-Stream and AXI4 Master Interfaces
Learn how you can map your DUT ports to multiple AXI4-Stream, AXI4-Stream Video, and AXI4 Master interfaces. - IP Core Reset Interface
Learn how HDL Coder automatically inserts logic to synchronize global reset signal to IP core clock domain. - IP Core Clock Interface
Configure clock inputs for generated IP cores. - IP Core Generation Workflow for Standalone FPGA Devices
Learn how to use the IP Core Generation workflow with standalone FPGA devices and embed the IP core into the reference design. - Deploy IP Core With Auto-Generated Reference Design
Generate and deploy an IP core to an AMD SoC board without selecting or authoring a pre-existing reference design. (自 R2026b 起)
AMD SoC 参考设计
- Default System Reference Design for AMD FPGA Board (SoC Blockset)
Learn about the default system reference design for AMD FPGA board and using the reference design. - Default System Reference Design for AMD SoC Devices (SoC Blockset)
Learn about how to use Default system reference design and its requirements. - Default Video System Reference Design (SoC Blockset)
Learn about the default video system reference design and its requirements. - Reference Designs for RFSoC Devices (SoC Blockset)
Learn about how to use RFSoC reference designs and their requirements.
Intel SoC 参考设计
- Default System Reference Design for Altera SoC Devices
Learn about the default system reference design and using the reference design for Altera SoC Devices. - Default System with External DDR4 Memory Access Reference Design
Learn about the default system with external DDR3 memory access reference design and its requirements.
Microchip SoC 参考设计
- Default System Reference Design
Learn about the default system reference design and using the reference design.
参考设计集成
- IP Caching for Faster Reference Design Synthesis
Use IP caching to speed up reference design synthesis time by using an out-of-context workflow. - Resolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows
Resolve timing failures in Build FPGA Bitstream step of IP Core Generation Workflow or Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards.
精选示例
Generate IP Core from Multirate Model
Learn various example designs that use multiple sample rates with IP Core Generation workflow.
Generate IP Core with Multiple AXI4-Stream Channels
Model an audio system with multiple AXI4-Stream channels and deploy it on a ZedBoard™ by using an audio reference design.
Integrate HDL IP Core with Versal AI Engine
Model, partition, and deploy a design that leverages the processor, FPGA, and AI Engines on a Versal device.
Getting Started with Targeting Xilinx Versal Adaptive SoC Platform
Use HDL Coder™ and the hardware-software co-design workflow to blink LEDs at various frequencies on the Xilinx® Versal® Adaptive SoC platform.
