运行和验证生成的 IP 核

在目标 FPGA 器件上原型化、仿真和验证生成的 IP 核

在目标硬件上运行和验证从 IP 核设计生成的比特流。输入是器件上 FPGA 部分的生成比特流。输出是在目标 FPGA 上运行的经过仿真和验证的设计。有关工作流的更多详细信息，请参阅Targeting FPGA & SoC Hardware Overview。

Run and Verify IP Core on Target Hardware Workflow

对象

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FPGA I/O

`fpga`	Data transfer object to enable data read and write operations from MATLAB to target FPGA or SoC device
`hdlcoder.DUTPort`	DUT port from an HDL Coder generated IP core, saved as an object array
`xilinxsoc`	Connection to processor on Xilinx SoC board to perform basic Linux shell operations or program the board (自 R2022a 起)
`intelsoc`	Connection to processor on Intel SoC board to perform basic Linux shell operations or program the board (自 R2022a 起)

函数

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FPGA I/O

`addAXI4SlaveInterface`	Write data to IP core or read data from IP core using AXI4 or AXI4-Lite interface
`addAXI4StreamInterface`	Write data to IP core or read data from IP core using AXI4-Stream interface
`addMemoryInterface`	Access memory regions on your FPGA or SoC hardware (自 R2023a 起)
`mapPort`	Maps a DUT port to specified AXI4 interface in HDL IP core
`writePort`	Write data to a DUT port from MATLAB
`readPort`	Reads output data and returns it with the port data type and dimension
`writeMemory`	Write data to memory regions on FPGA or SoC hardware (自 R2023a 起)
`readMemory`	Read data from memory regions on FPGA or SoC hardware (自 R2023a 起)
`readMemoryOffset`	Read data from memory regions on FPGA or SoC hardware by using offset address (自 R2023b 起)
`writeMemoryOffset`	Write data to memory regions on FPGA or SoC hardware by using the offset address (自 R2023b 起)
`release`	Release the hardware resources associated with the fpga object
`system`	Run command in Linux shell on SoC board (自 R2022a 起)
`getFile`	Transfer file from SoC board to host computer (自 R2022a 起)
`putFile`	Transfer file from host computer to SoC board (自 R2022a 起)
`deleteFile`	Delete file on SoC board (自 R2022a 起)
`dir`	List directory contents on SoC board (自 R2022a 起)
`programFPGA`	Program FPGA and set corresponding device tree from processor on SoC board (自 R2022a 起)

主题

Program Target FPGA Boards or SoC Devices
How to program the target Intel or Xilinx Hardware.
Choose a Method to Interact with IP Cores on Target Hardware
Choose a software interface method to interact with IP cores running on target hardware.
Generate and Manage FPGA I/O Host Interface Scripts
Understand what a host interface script is and learn how to generate and manage host interface scripts.
Use FPGA I/O to Rapidly Prototype HDL IP Core
Create and author a host interface script by configuring interfaces and port mapping information to control HDL IP core.
Debug and Control Generated HDL IP Core by Using JTAG AXI Manager
Specify automatic insertion of the HDL Verifier AXI Manager IP into a reference design.
Debug AXI4 Slave Registers Using Readback in Generated IP Cores
This example describes the different techniques to read the AXI4 slave input registers in your design.
Debug IP Core Using FPGA Data Capture
This example shows how to debug an IP core you generate in HDL Coder™ using only FPGA Data Capture as well as both AXI Manager and FPGA Data Capture together.
Model and Debug Test Point Signals with HDL Coder
An example that shows how to add test points to signals in your model and debug these signals in the generated HDL code.
Debug IP Core Using Hardware-Software Deployment
Debug a Zynq^® design using HDL Coder™ and Embedded Coder^® features.
Prototype IP Core on Zynq with MATLAB FPGA I/O Host Interface
Implement a QPSK communication algorithm on a AMD^® Zynq radio using MATLAB for signal transmission and reception.

精选示例

Prototype Generated IP Core on Hardware using FPGA I/O

Use MATLAB® to prototype an algorithm running on FPGA hardware from your host computer. The example demonstrates the workflow on the Versal AI Core Series VCK190 Evaluation Kit, but can be run on any Xilinx® Zynq®, UltraScale+™, or Versal® board supported by HDL Coder.

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Use FPGA I/O to Communicate with FPGA on Zynq-Based Radio by Using MATLAB

Prototype an FPGA design on a Xilinx® Zynq®-based radio and communicate with hardware by using MATLAB® as the host computer. In this example, you can deploy a waveform transmitter and receiver algorithm on hardware, and then transmit and receive the stream signals through the MATLAB® host.

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