用于软硬件部署的 IP 核生成
从软件接口模型生成 C 代码（需要 Embedded Coder®），并使用外部模式或处理器在环 (PIL) 模式在目标硬件上部署和运行软硬件模型。输入是 SoC 器件的可部署模型，包括：
从包含 HDL IP 核的原始模型生成的比特流。
软件接口模型，其中包含配置的设备驱动以允许处理器和 FPGA 之间的通信以及嵌入式处理器的 C 代码生成。
输出是在目标硬件上运行的软硬件器件的生成代码。
有关工作流的更多详细信息，请参阅Targeting FPGA & SoC Hardware Overview。
主题
- Choose a Method to Interact with IP Cores on Target Hardware
Choose a software interface method to interact with IP cores running on target hardware.
- Processor and FPGA Synchronization
In the HDL Workflow Advisor, you can choose a Processor/FPGA synchronization mode for your processor and FPGA when you generate a custom IP core to use in an embedded system integration project.
精选示例
Basic Control Algorithm Partitioned into FPGA and ARM
Models a field-oriented controller (FOC) for a permanent magnet synchronous machine (PMSM) on the AMD Zynq® UltraScale+™ MPSoC target. This example uses the Trenz Electronic™ Motor Control Development Kit TE0820 revision 4. If you do not have the required hardware, you can use this example to help you develop a controller for your own hardware configuration.
