configureADCTileClock

Configure output clock frequency of ADC tile

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Syntax

configureADCTileClock(rfDataConverter,tileId,resampleFactor)

Description

Add-On Required: This feature requires the HDL Coder Support Package for AMD FPGA and SoC Devices add-on.

configureADCTileClock(rfDataConverter,tileId,resampleFactor) configures the frequency of the output clock of the specified ADC tile for the provided resample factor.

Input Arguments

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RF data converter, specified as an soc.RFDataConverter object. Via Ethernet, this object connects the host computer to the RF data converter on the connected SoC device. Use the object functions and properties of this object to configure the RF data converter.

Identifier of the RF-ADC tile connected to the programmable logic, specified as 0, 1, 2, or 3. Available options for the RF-ADC tile ID vary according to the specified RFSoC device. A tile contains several ADCs, accessible as channels, and several shared timing units, including a clock and PLL.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64

Resample factor of the shared clock for the RF-ADC tile, specified as a nonnegative integer.

Data Types: double

Version History

Introduced in R2020b

See Also

Functions

External Websites