AXI Manager Read
Read memory locations on FPGA board from Simulink
Libraries:
HDL Verifier Support Package for Intel Boards
HDL Verifier Support Package for AMD FPGA and SoC Devices
Description
The AXI Manager Read block communicates with the AXI manager IP when it is running on an FPGA board. The block forwards read commands to the IP to access memory-mapped locations on the FPGA board.
Note
The AXI Master Read block has been renamed to AXI Manager Read block. For more information, see Version History.
Before using this block, you must create an AXI manager IP and integrate it in your FPGA design. For more information, see Set Up AXI Manager.
Ports
Output
data — Data read from FPGA board
scalar | vector
Data read from the FPGA board, returned as a scalar or vector. The output is of
size 1-by-N
, where N
is the
Output vector size parameter value. The Output data
type parameter sets the data type of this output. The read data from the
FPGA is of type uint32
, int32
,
uint64
, or int64
depending on the data width
of the AXI manager IP on your FPGA. The block converts the data type to the value
specified by the Output data type parameter.
Data Types: uint8
| int8
| uint16
| int16
| half
| uint32
| int32
| single
| uint64
| int64
| double
| fixed point
Parameters
Main
Address — Starting address for read operation
0
(default) | nonnegative integer multiple of 4 or 8 | nonnegative hexadecimal value multiple of 4 or 8
Specify the starting address for the read operation as a nonnegative integer or
hexadecimal value. The block supports the address width of 32, 40, and 64 bits. The
block converts the address data type to uint32
or
uint64
according to the AXI manager IP address width. The address
must refer to an AXI subordinate memory location controlled by the AXI manager IP on
your FPGA board.
Memory Mapping Guidelines
If the AXI manager IP data width is 32 bits, the memory is 4 bytes aligned, and each address is a 4-byte increment (
0x0
,0x4
,0x8
). For example the address0x1
returns an error.If the AXI manager IP data width is 64 bits, the memory is 8 bytes aligned, and each address is an 8-byte increment (
0x0
,0x8
,0x10
). For example, specifying the address0x1
or0x4
are both invalid and return an error.If the AXI manager IP data width is 32 bits and the Burst type parameter is set to
Increment
, the block increments the address by 4 bytes.If the AXI manager IP data width is 64 bits and the Burst type parameter is set to
Increment
, the block increments the address by 8 bytes.If the AXI manager IP data width is 32 bits and the Output data type parameter is set to
half
, the block reads the lower 2 bytes and ignores the higher 2 bytes.If the AXI manager IP data width is 64 bits and the Output data type parameter is set to
half
, the block reads the lower 2 bytes and ignores the higher 6 bytes.Do not use a 64-bit AXI manager IP for accessing 32-bit registers.
Example: 0xa4
Burst type — AXI4 burst type
Increment
(default) | Fixed
In Increment
mode, the AXI manager reads a vector of
data from contiguous memory spaces starting with the specified address. In
Fixed
mode, the AXI manager reads all data from the same address.
Note
The Fixed
burst type is not supported for the
PCI Express® interface. Use the Increment
burst type
instead.
Output data type — Data type of the output data
uint32
(default) | double
| single
| half
| int8
| uint8
| int16
| uint16
| int32
| int64
| uint64
| fixdt(1,16,0)
| <data type expression>
The block converts the data read out of the FPGA to the specified data type.
Output vector size — Number of memory locations to read
1
(default) | positive integer
Specify the number of memory locations for the block to read. By default, the
block reads from a contiguous address block, incrementing the address for each
operation. To turn off address increment mode and read repeatedly from the same
location, set the Burst type parameter to
Fixed
.
When you specify a large operation size, such as reading a block of double data rate (DDR) memory, the block automatically breaks the operation into multiple bursts, using the maximum supported burst size. The maximum supported burst size is 256 words.
Sample time — Read sample time
-1
(default) | positive scalar
Specify the simulation sample time for the block. When you specify
-1
(default), the block inherits the sample time from other
blocks in the system.
Vector register data with strobe synchronization — Read data from registers with strobe synchronization
off
(default) | on
To enable reading data from a set of registers with strobe synchronization, select this parameter. Enable this parameter when your FPGA design includes strobe synchronization generated by HDL Coder™. For more information about strobe synchronization, see the "Vector Data Read/Write with Strobe Synchronization" section in IP Core User Guide (HDL Coder).
Strobe address — Strobe address used for strobe synchronization
0
(default) | nonnegative integer multiple of 4 or 8 | nonnegative hexadecimal value multiple of 4 or 8
Set the absolute address for the strobe generated with HDL Coder. The absolute address is the sum of the base address and the strobe offset provided by the IP core report.
Example: If the base address is 0x41000000
and offset is
0x110
, the absolute address is
0x41000110
.
Dependencies
To enable this parameter, select Vector register data with strobe synchronization.
Interface
Type — Type of interface used for communication with FPGA board
JTAG
(default) | PCIe
| PL Ethernet
| PS Ethernet
| USB Ethernet
Specify the interface type for communicating between the host and the FPGA.
Note
AXI manager supports the PS Ethernet and USB Ethernet interfaces for only the AMD® Zynq® devices.
AXI Manager Interface Configuration
To view these parameters, open the AXI Manager Interface Configuration dialog box by clicking Configure global parameters. The visible parameters depend on the Type parameter value.
Global parameters apply to the entire Simulink® model.
Vendor — FPGA brand name
Intel
| AMD
Specify the manufacturer of your FPGA board. The AXI manager IP varies depending on the FPGA board type.
Dependencies
To enable this parameter, click Configure global parameters.
AXI data width — Data width of AXI manager IP on FPGA
32
(default) | 64
Select the data width, in bits, of the AXI manager IP on the FPGA.
For PCI Express, PS Ethernet, or USB Ethernet, set this value to
32
. For JTAG or PL Ethernet, set this value to
32
or 64
.
Dependencies
To enable this parameter, click Configure global parameters.
Cable type — Type of JTAG cable used for communication with FPGA board (AMD only)
auto
(default) | FTDI
Specify the type of JTAG cable used for communication with the FPGA board. Use this parameter when more than one cable is connected to the host computer.
When you set this parameter to auto
(default), the block
automatically detects the JTAG cable type. The block prioritizes searching for Digilent® cables and uses this process to detect the cable type.
The AXI Manager Write block searches for a Digilent cable. If the block finds:
Exactly one Digilent cable, it uses that cable for communication with the FPGA board.
More than one Digilent cable – it returns an error. To resolve this error, specify the desired cable using the Cable name parameter.
No Digilent cables, it searches for an FTDI cable.
If no Digilent cable is found, the AXI Manager Write block searches for an FTDI cable. If the block finds:
Exactly one FTDI cable, it uses that cable for communication with the FPGA board.
More than one FTDI cable, it returns an error – To resolve this error, specify the desired cable using the Cable name parameter.
No FTDI cables, it returns an error – To resolve this error, connect a Digilent or FTDI cable.
If it finds two cables of different types, it prioritizes the Digilent cable. To use an FTDI cable, set this parameter to
FTDI
.
When you set this parameter to FTDI
, the block searches for
FTDI cables. If the object finds:
Exactly one FTDI cable, it uses that cable for communication with the FPGA board.
More than one FTDI cable, it returns an error – To resolve this error, specify the desired cable using the Cable name parameter.
No FTDI cables, it returns an error – To resolve this error, connect a Digilent or FTDI cable.
For more details, see Select from Multiple JTAG Cables for AMD Boards.
Dependencies
To enable this parameter, set Type to
JTAG
and Vendor to
AMD
.
Cable name — Name of JTAG cable used for communication with FPGA board
auto
(default) | name of connected JTAG cable
Specify this parameter if more than one JTAG cable of the same type are connected to the host computer. If more than one JTAG cable is connected to the host computer, and you do not specify this parameter, the block returns an error. The error message contains the names of the available JTAG cables. For more details, for Intel® boards, see Select from Multiple JTAG Cables for Intel Boards. For AMD boards, see Select from Multiple JTAG Cables for AMD Boards.
Dependencies
To enable this parameter, set Type to JTAG
.
Clock frequency in MHz — JTAG clock frequency
15
(default) | positive scalar
Specify the JTAG clock frequency in MHz. The JTAG frequency depends on the type of cable and the maximum clock frequency supported by the FPGA board. Check the board documentation for the supported frequency range.
Dependencies
To enable this parameter, set Type to JTAG
.
Chain position — Position of FPGA in JTAG chain (AMD only)
auto
(default) | nonnegative integer
Specify this parameter value as a nonnegative integer if more than one FPGA or
Zynq device is on the JTAG chain. Otherwise, select auto
(default) for automatic detection of chain position.
Dependencies
To enable this parameter, set Type to
JTAG
and Vendor to
AMD
.
Instruction registers before FPGA — Sum of instruction register lengths for all devices before target FPGA (AMD only)
0
(default) | nonnegative integer
Specify this parameter value as a nonnegative integer if more than one FPGA or Zynq device is on the JTAG chain.
Dependencies
To enable this parameter, set Type to
JTAG
and Vendor to
AMD
.
Instruction registers after FPGA — Sum of instruction register length for all devices after target FPGA (AMD only)
0
(default) | nonnegative integer
Specify this parameter value as a nonnegative integer if more than one FPGA or Zynq device is on the JTAG chain.
Dependencies
To enable this parameter, set Type to
JTAG
and Vendor to
AMD
.
Device address — IP address of Ethernet port or USB Ethernet gadget on FPGA board
dotted quad value
Specify the IP address of the Ethernet port or USB Ethernet gadget on the FPGA board.
The target IP address must be a set of four numbers consisting of integers in the range [0,
255] that are separated by dots. The default IP address for the PL Ethernet or PS Ethernet
interface is 192.168.0.2
. The default IP address for the USB Ethernet
interface is 192.168.1.2
.
Example: 192.168.0.10
Dependencies
To enable this parameter, set Type to PL
Ethernet
, PS Ethernet
, or USB
Ethernet
.
Port — UDP port number of FPGA board
50101
(default) | integer from 255 to 65,535
Specify the user datagram protocol (UDP) port number of the target FPGA as an integer from 255 to 65,535.
Dependencies
To enable this parameter, set Type to PL
Ethernet
.
Version History
Introduced in R2019bR2024a: Support for USB Ethernet
The AXI Manager Read block supports the USB Ethernet interface for an
AMD
Zynq board. To use this interface, on the Interface tab, set
Type to USB Ethernet
.
R2024a: PL Ethernet or PS Ethernet replaces Ethernet interface
The PL Ethernet or PS Ethernet interface replaces the Ethernet interface. To select the
Ethernet interface, on the Interface tab, set Type
to PL Ethernet
or PS Ethernet
depending on your hardware board. The Ethernet
interface type is
removed.
R2023b: UDP renamed to Ethernet
The UDP interface is renamed to the Ethernet interface. To select the Ethernet
interface, on the Interface tab, set Type to
Ethernet
. The UDP
interface type is
removed.
R2023a: Support for half data type
The block reads half
data from the memory locations on the FPGA
board. The address for the read operation must refer to an AXI subordinate memory location
controlled by the AXI manager IP on your FPGA board.
If the AXI manager IP data width is 32 bits, the memory is 4 bytes aligned, and addresses have 4-byte increments (
0x0
,0x4
,0x8
). In this case, the block reads the lower 2 bytes and ignores the higher 2 bytes.If the AXI manager IP data width is 64 bits, the memory is 8 bytes aligned, and addresses have 8-byte increments (
0x0
,0x8
,0x10
). In this case, the block reads the lower 2 bytes and ignores the higher 6 bytes.
R2022a: AXI Master Read renamed to AXI Manager Read
The AXI Master Read block has been renamed to the AXI Manager Read block. In the software and documentation, the terms "manager" and "subordinate" replace "master" and "slave," respectively.
In R2022a, you cannot use a Simulink model that contains the AXI Master Read block. Recreate your model in R2022a by using the AXI Manager Read block.
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