setCaptureCondition

Configure comparison for each signal value

Since R2024a

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Syntax

setCaptureCondition(hub,signalName,enable,signalValue)
setCaptureCondition(hub,signalName,enable,signalValue,DataCaptureName=dataCaptureIPName)

Description

setCaptureCondition(hub,signalName,enable,signalValue) configures a capture value comparison for the signal signalName for the first data capture IP. hub is a customized data capture hub object. The enable argument indicates whether this signal is part of the overall capture condition.

example

setCaptureCondition(hub,signalName,enable,signalValue,DataCaptureName=dataCaptureIPName) configures a capture value comparison for the signal signalName, for a data capture IP specified by dataCaptureIPName.

Examples

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This example uses a customized data capture hub object, hub, that connects with two data capture IPs. The first data capture IP is datacapture1 and the second data capture IP is datacapture2. Each IP defines two signals for both trigger and data capture. Signal A is 1 bit and signal B is 8 bits.

Enable capture condition logic for the datacpture1 IP.

setEnableCaptureCtrl(hub,true);

To enable capture condition logic, you must select the Include capture condition logic parameter while generating the data capture IPs using the FPGA Data Capture Component Generator tool.

Enable capture condition logic for the datacpture2 IP.

setEnableCaptureCtrl(hub,true,DataCaptureName="datacapture2");

Set up a capture condition to capture data when the FPGA detects a high value on signal A and a value 17 on signal B. Set this condition for the datacapture1 IP.

setCaptureCondition(hub,'A',true,'High');
setCaptureCondition(hub,'B',true,uint8(17));

Set up a capture condition to capture data when the FPGA detects a high value on signal A. Set this condition for the datacapture2 IP.

setCaptureCondition(hub,'A',true,'High',DataCaptureName="datacapture2");

Input Arguments

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Data capture hub object that interacts with each data capture IP, specified as a dataCaptureHub object.

Name of the capture component signal, specified as a character vector.

This name must match one of the signal names configured on creation of the data capture IPs using the FPGA Data Capture Component Generator tool. The signal must be configured as a possible trigger signal.

Data Types: char

Indication that the signal is part of the capture condition, specified as true or false. To use this signal in the overall capture condition, set this value to true. When you set this value to false, the signal is not used for the overall capture condition.

Value to compare the signal to as part of the capture condition, specified as one of the following.

  • Decimal, binary, or hexadecimal value — For a multibit signal, specify a value within the range of the data type associated with the signal. If you specify a binary or hexadecimal value, you can use an X or x to indicate signals for the function to ignore during the value comparison.

    To separate a group of bits for better readability, you can use _ between bits. For example, you can represent a 32-bit binary value as '0b1010_XXXX_1011_XXXX_1110_XXXX_1111XXXX' and a 32-bit hexadecimal value as '0xAB_CDEXFX'.

  • 'Low', 'High', 'Rising edge', 'Falling edge', or 'Both edges' — For a logical signal, specify a string that indicates the level or edge to match. For more information, see Capture Conditions.

Name of the data capture IP, specified as a character vector or string scalar. The default value for this argument is "generatedIPName1", where generatedIPName1 is the name of the first data capture IP set by the Generated IP name parameter of the FPGA Data Capture Component Generator tool.

Version History

Introduced in R2024a

See Also

Objects

Tools