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setEnableCaptureCtrl

Enable or disable capture condition logic

Since R2024a

Description

setEnableCaptureCtrl(hub,value) enables or disables capture condition logic for the first data capture IP connected to the hub data capture hub object based on a value specified by value.

To enable capture condition logic, you must select the Include capture condition logic parameter while generating the data capture IPs using the FPGA Data Capture Component Generator tool.

example

setEnableCaptureCtrl(hub,value,DataCaptureName=dataCaptureIPName) configures capture condition logic for a data capture IP specified by dataCaptureIPName.

Examples

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This example uses a customized data capture hub object, hub, that connects with two data capture IPs. The first data capture IP is datacapture1 and the second data capture IP is datacapture2. Each IP defines two signals for both trigger and data capture. Signal A is 1 bit and signal B is 8 bits.

Enable capture condition logic for the datacpture1 IP.

setEnableCaptureCtrl(hub,true);

Enable capture condition logic for the datacpture2 IP.

setEnableCaptureCtrl(hub,true,DataCaptureName="datacapture2");

Input Arguments

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Data capture hub object that interacts with each data capture IP, specified as a dataCaptureHub object.

Set this argument to true to enable capture condition logic in a data capture IP. Enable capture condition logic to use a capture condition to control which data to capture from the FPGA. The data capture IP evaluates the capture condition at each clock cycle and captures only the data that satisfies the capture condition. For more information on capture conditions, see Capture Conditions.

Name of the data capture IP, specified as a character vector or string scalar. The default value for this argument is "generatedIPName1", where generatedIPName1 is the name of the first data capture IP set by the Generated IP name parameter of the FPGA Data Capture Component Generator tool.

Version History

Introduced in R2024a