Main Content

launchVCS

Start and configure Synopsys VCS simulator for use with HDL Verifier software

Since R2024b

collapse all in page

    Syntax

    launchVCS(VerilogFiles=files,HDLTopLevelName=topModule);
    launchVCS(VHDLFiles=files,HDLTopLevelName=topModule);
    launchVCS(VerilogFiles=files,VHDLFiles=files,HDLTopLevelName=topModule);
    launchVCS(__,Name=Value);

    Description

    launchVCS(VerilogFiles=files,HDLTopLevelName=topModule); performs these actions:

    • Generates HDL compilation scripts for VCS®

    • Generates VCS simulator launch scripts

    • Compiles Verilog® and starts the VCS simulator

    The scripts set up the GCC environment and load the correct HDL Verifier™ library into the Synopsys® VCS simulator.

    To generate custom scripts, use launchVCS to generate a shell script template (.sh). Then, perform one of the following actions:

    • Modify the template and run it from the MATLAB® command prompt by using a system command.

    • Invoke the script directly from a shell.

    In batch mode, the function returns only after launching and starting the HDL simulator. In interactive mode, the function returns without waiting for the HDL simulator to start.

    example

    launchVCS(VHDLFiles=files,HDLTopLevelName=topModule); generates HDL compilation scripts and simulation launch scripts, then compiles the VHDL® files and starts the VCS simulator.

    example

    launchVCS(VerilogFiles=files,VHDLFiles=files,HDLTopLevelName=topModule); generates HDL compilation scripts and simulation launch scripts for a mixed-language design. Then, the function compiles the HDL files and starts the VCS simulator.

    launchVCS(__,Name=Value); specifies options using one or more name-value arguments in addition to the input arguments in previous syntaxes.

    Examples

    collapse all

    Compile and launch a single-file Verilog design for cosimulation with Simulink®. Allow use of Verilog-2000 syntax in the HDL source. Then, launch Synopsys VCS.

    launchVCS( ...
        VerilogFiles="myinverter.v", ...
        VloganFlags="+v2k", ...
        HDLTopLevelName="myinverter" ...
       );

    Compile and launch a VHDL design in batch mode.

    In batch mode, the VCS simulator exits after the simulation completes. Relaunch the simulation by calling launchVCS again with the SkipScriptGeneration and SkipCompilation arguments.

    coreLaunchArgs={"VHDLFiles",["foo1.vhd","foo2.vhd"],"HDLTopLevelName","top","RunMode","batch" };
 
launchVCS(...
        coreLaunchArgs{:},...
        "SkipScriptGeneration",    true,...
        "SkipCompilation",         true...
       );

    Input Arguments

    collapse all

    Name-Value Arguments

    Specify optional pairs of arguments as Name1=Value1,...,NameN=ValueN, where Name is the argument name and Value is the corresponding value.

    Example: launchVCS(VerilogFiles="myinverter.v",HDLTopLevelName="myinverter");

    You must specify HDLTopLevelName, and VerilogFiles or VHDLFiles. Specify both for a mixed language design.

    Location of the Verilog files, specified as a string or string array of file names. Specify the location as a full path, or relative to the RunDirectory location.

    Data Types: string

    Location of the VHDL files, specified as a string or as a string array of file names. Specify the location as a full path, or relative to the RunDirectory location.

    Data Types: string

    Name of the HDL top-level module, specified as a string scalar.

    Data Types: string

    Location to run the HDL simulator, specified as a folder path.

    The following conditions apply to this argument:

    • If the specified directory does exist, the function creates this directory for you.

    • White spaces are not supported.

    Data Types: string | char

    Run mode for the HDL simulator, specified as the comma-separated pair consisting of 'RunMode' and one of the following values:

    • batch – Starts the HDL simulator in the background with no window.

    • batch-with-terminal – Starts the HDL simulator in the background and shows the session in a terminal.

    • cli – Starts the HDL simulator in an interactive shell.

    • gui – Starts the HDL simulator with Synopsys DVE graphical user interface.

    Flags which are specific for vlogan – the VCS Verilog analysis stage, specified as a string.

    Data Types: string

    Flags which are specific for vhdlan – the VCS VHDL analysis stage, specified as a string.

    Data Types: string

    Path to the signal access file, specified as a string. The files specifies which signals have read/write/force access to the cosimulation application. See your Synopsys VCS documentation on how to create this file.

    vcs compilation and elaboration flags.

    simv runtime flags.

    Tcl commands to execute before starting the HDL simulation. For example, you can specify simple waveform generation statements for signals such as clocks, resets, and enables.

    Example: PreSimulationTcl=["force UDelay.clk 1 0, 0 5 -repeat 10","force UDelay.reset 1 0, 0 5"]

    Tcl commands to execute after finishing the HDL simulation.

    Specify the number of seconds to wait for the HDL simulator to start before reporting an error. To avoid waiting for the simulator to start, use the value 0.

    Dependencies

    This argument is valid only when you set RunMode to batch or batch-with-terminal.

    String array of HDL Cosimulation block instances to use in cosimulation.

    When you do not specify this argument, all cosimulation blocks in current model are used.

    Dependencies

    This argument is for Simulink cosimulation only.

    Specify the communications mechanism between Simulink and VCS:

    • automatic-port — Find an available TCP port on the current host and program the HDL Cosimulation blocks specified by CosimulationBlockList with that port.

    • block-property — Use the communication parameters in the cosimulation block mask.

    • port number — Program the HDL Cosimulation blocks specified by CosimulationBlockList with a numeric socket port value, specified as a string.

    Dependencies

    This argument is for Simulink cosimulation only.

    String array of environment variables for use by the compilation and launch scripts. Specify as VAR=value, where VAR is the variable name, and value is the assigned value.

    Do not write compilation and launch scripts.

    Data Types: logic

    Do not execute the compilation script.

    Data Types: logic

    Do not execute the launch script.

    Data Types: logic

    Path to the HDL Verifier HDL libraries. If you do not specify this argument, the function uses the default path in the MATLAB installation.

    Specify the version of GCC to use:

    • default — Use the same compiler that MATLAB uses.

    • vg-gnu-gcc-9.5.0 — Use VG-GNU compiler.

    Path to nondefault VG_GNU_PACKAGE, specified as a string. You must specify this argument to compile your files when:

    • You are using a nondefault GCC version.

    • Your installation of VG_GNU_PACKAGE is not in the default location (outside the VCS tree).

    Dependencies

    The GCCVersion argument must be set to vg-gnu-gcc-9.5.0.

    Version History

    Introduced in R2024b

    See Also

    Topics