Simulink Cosimulation

Cosimulate HDL code with Simulink^®

To get started, see Verify HDL Module with Simulink Testbench.

Blocks

HDL Cosimulation	Cosimulate HDL design by connecting Simulink with HDL simulator
To VCD File	Generate value change dump (VCD) file

Apps

HDL Verifier	Generate HDL verification artifacts and follow verification workflows from a Simulink subsystem (Since R2020b)
Cosimulation Wizard	Generate a cosimulation block or System object from existing HDL files

Functions

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Startup

`nclaunch`	Start and configure Cadence Xcelium simulator for use with HDL Verifier software
`vsim`	Start and configure ModelSim for use with HDL Verifier
`launchVCS`	Start and configure Synopsys VCS simulator for use with HDL Verifier software (Since R2024b)

HDL-Simulator Commands

`hdlsimulink`	Load instantiated HDL module for cosimulation with Cadence Xcelium and Simulink
`vsimulink`	Load instantiated HDL module for cosimulation with ModelSim and Simulink

Server Control

`breakHdlSim`	Execute `stop` command in HDL simulator from MATLAB
`pingHdlSim`	Block cosimulation until HDL simulator is ready
`tclHdlSim`	Execute Tcl command in Xcelium or ModelSim simulator

Objects

cosimulationConfiguration Configure HDL cosimulation workflow (Since R2022b)

Topics

Startup and Connection

Set Up for HDL Cosimulation
To cosimulate your HDL code with a MATLAB^® or Simulink design, you must first:
Supported EDA Tools and Hardware
List of supported third-party EDA software and FPGA boards.
Start HDL Simulator for Cosimulation in Simulink
Set up the connection between the HDL simulator and Simulink.
TCP/IP Socket Ports
Provides some direction for choosing TCP/IP socket ports.
Cross-Network Cosimulation
Provides instructions for performing cosimulation across a local network.

Testbench

Get Started with Simulink HDL Cosimulation
Set up an HDL Verifier™ application using the Cosimulation Wizard in the Simulink® environment.
Simulink as a Testbench
Provides an introduction to the process for integrating HDL Verifier™ blocks into a Simulink design.
Create a Simulink Cosimulation Testbench
The steps to code and run a Simulink-as-testbench cosimulation for use with the HDL Verifier software.
Verify HDL Module with Simulink Testbench
Set up an HDL Verifier session that uses Simulink to verify a simple VHDL^® model.

Verification of Generated HDL Code with Cosimulation Testbench (requires HDL Coder license)

Generate Test Bench and Enable Code Coverage Using the HDL Workflow Advisor (HDL Coder)
Generate test bench and code coverage for generated HDL code using the HDL Workflow Advisor.
Automatic Verification of Generated HDL Code from Simulink
Verify generated HDL code using a generated cosimulation model.

Component Algorithm

Component Simulation with Simulink
Provides an introduction to the process for integrating blocks into a Simulink design.
Create Simulink Model for Component Cosimulation
Provides a high-level view of the steps involved in coding and running a Simulink-as-component cosimulation for use with the software.

Cosimulation with Simulink

HDL Cosimulation
The HDL Verifier software consists of MATLAB functions, a MATLAB System object™, and a library of Simulink blocks, all of which establish communication links between the HDL simulator and MATLAB or Simulink.
Performing Cosimulation
Next steps after you generate a function or block representing your HDL module.
Prepare to Import HDL Code for Cosimulation
Prepare for cosimulation and choose whether to cosimulate your HDL code as a function, System object, or block.
Import HDL Code for HDL Cosimulation Block
Generate a Simulink block to cosimulate your HDL code.
Run a Simulink Cosimulation Session
Run your testbench or algorithm, including the cosimulation of your HDL module.
Relocate HDL Cosimulation Design Support Files
Relocate your HDL Cosimulation design support files for model sharing.
Use HDL Parameters in Cosimulation
Use Verilog parameters or VHDL generics in cosimulation.

HDL Simulator Interaction

Simulation Timescales
The representation of simulation time differs significantly between the HDL simulator and Simulink.
Clock, Reset, and Enable Signals
You can create rising-edge or falling-edge clocks, resets, or clock enable signals that apply internal stimuli to your model under cosimulation.
Simulation Speed Improvement Tips
Provides suggestions for optimizing your cosimulation performance.
Frame-Based HDL Cosimulation
Frame-Based processing for HDL Cosimulation.
Supported Data Types
If your HDL application needs to send HDL data to a MATLAB function or a Simulink block, you may first need to convert the data to a type supported by MATLAB and the HDL Verifier software.
Race Conditions in HDL Simulators
Describes ways to avoid race conditions in hardware cosimulations with MATLAB and Simulink software.

Recording Signal State Transitions for Post-Processing

Add a Value Change Dump (VCD) File
A value change dump (VCD) file logs changes to variable values, such as the values of signals, in a file during a simulation session.
Visually Compare Simulink Signals with HDL Signals
Guides you through the basic steps for adding a To VCD File block to a Simulink model for use with cosimulation.

Featured Examples

Verify Viterbi Decoder Using HDL Cosimulation

Generate and verify HDL code to implement a fixed-point Viterbi decoder.

Open Script

Timescales: Absolute, Relative and Automatic

Illustrates the various Timescale settings within the HDL Cosimulation block and explains how these affect the timing relationship of Simulink® and the HDL simulator. We use a simple Verilog parity check model to show the timing relationship of Simulink and the HDL simulator (ModelSim® or Xcelium™) used for cosimulation.

Open Model

Frame-Based Scrambler Using Communications Toolbox

Illustrates the validation of an HDL implementation of a 6-order scrambler. A scrambler is used in communication systems to randomize transitions in the transmitted signal by shuffling the bits. One purpose of scrambling is to reduce the length of strings of 0s or 1s in a transmitted signal, since a long string of 0s or 1s may cause transmission synchronization problems. Scrambling may also be used as a cheap encryption technique. This example consists of two models. The first model scrambler_frame validates the HDL implementation and the second model scrambler_fsk uses the HDL scrambler as part of a communication channel.

Open Script

Cosimulate Vivado FFT IP Core with Simulink

Using HDL Verifier™, you can set up cosimulation between Simulink® and an IP core from the AMD® Vivado® simulator. This setup allows you to design your Simulink algorithm to include an AMD IP implementation in the system and use Simulink as a testbench. To verify the IP core, you can use the specialized stimulus and visualization scopes from Simulink.

Open Script

Batch Mode Cosimulation of Manchester Receiver

Illustrates using MATLAB® to start HDL simulator in batch mode and performing cosimulation with Simulink® using the HDL Verifier™ HDL Cosimulation block.

Open Script

Manchester Receiver (Absolute Time Mode)

Verification of a Manchester encoder using HDL Verifier with Simulink. Manchester encoding is a simple modulation scheme that converts baseband digital data to an encoded waveform with no DC component. The most widely known application of this technique is Ethernet.

Open Script

Manchester Receiver Using Communications Toolbox

Verification of a Manchester encoder. Manchester encoding is a simple modulation scheme that converts baseband digital data to an encoded waveform with no DC component. The most widely known application of this technique is Ethernet.

Open Script

Manchester Receiver Using Multiple Cosimulation Blocks

Simulates a digital receiver of Manchester encoded data. Manchester encoding is a simple modulation scheme that converts baseband digital data to an encoded waveform with no DC component. The most widely known application of this technique is Ethernet.

Open Script

Manchester Receiver Using Mixed Design (Verilog and VHDL)

Verification of a Manchester encoder using mixed HDL languages, VHDL and Verilog. Manchester encoding is a simple modulation scheme which converts baseband digital data into an encoded waveform with no DC component. The most widely known application of this technique is Ethernet.

Open Script

Sobel Edge Detection Algorithm with Computer Vision Toolbox

Top-down design methodology applied to Sobel Edge Detection algorithm.

Open Script

Relating HDL Clocks and Resets with Simulink Sample Times

Illustrates the relationship of Simulink® sample times to HDL clocks and resets. The example uses HDL Verifier™ to cosimulate a synchronous Verilog parity check module. The example also contains the following:

Open Model

FPGA-Based Cell-Averaging Constant False Alarm Rate (CA-CFAR) Detector

Design a FPGA implementation-ready CA-CFAR detector.

(Phased Array System Toolbox)

FPGA-Based Monopulse Technique: Code Generation

Develop a monopulse technique to perform digital down-conversion (Part 2).

(Phased Array System Toolbox)

Validate and Accelerate Video Algorithm with Cosimulation and FPGA-in-the-Loop

Validate a video processing algorithm using cosimulation and accelerate this process using FPGA-in-the-loop (FIL). The process analyzes a simple system that sharpens an RGB video input at 24 frames per second (FPS). You enhance the RGB video feed using an FIR filter. Then, to validate the design, you leverage simulator-based and hardware-based verification features provided with HDL Verifier™ Toolbox.

Open Script

Get Started with Simulink HDL Cosimulation for Synopsys VCS

Cosimulate an HDL design with Simulink and Synopsys^® VCS^® simulator.

Open Live Script