HDL Verifier
Generate HDL verification artifacts and follow verification workflows from a Simulink subsystem
Description
The HDL Verifier app enables you to generate a SystemVerilog DPI component, an HDL Cosimulation block, or an FPGA-in-the-loop block from a Simulink® subsystem. The app also enables you to generate an FPGA Data Reader block that communicates with a generated IP core on an FPGA to return captured data into Simulink. The app then guides you through the workflow required to verify your HDL.
Select the HDL Verifier™ workflow on the left pane, under HDL Verifier Mode:
HDL Cosimulation — Select this option to generate an HDL Cosimulation block. Follow the toolstrip sections to prepare and run an HDL cosimulation, and then view the results.
DPI Component Generation — Select this option to generate a SystemVerilog DPI component. Follow the toolstrip sections to prepare and generate the component, and then view the results.
FPGA-in-the-Loop (FIL) — Select this option to generate an FIL Simulation block. Follow the toolstrip sections to load the design to your FPGA board, prepare and run a FIL simulation, and review the results.
FPGA Data Capture (FDC) — Select this option to capture signals from your FPGA design while the design runs on the FPGA. Click Generate FDC Components on the toolstrip to generate a data capture HDL IP core and an FPGA Data Reader block. Integrate the generated HDL IP core into your FPGA design and generate the bitstream. Then follow the toolstrip sections to load the bitstream, configure the data capture settings, run the model to capture data, and review the results.
Open the HDL Verifier App
Simulink Toolstrip: On the Apps tab, under Code verification, validation, and test, click HDL Verifier. The HDL Verifier app opens in its own tab on the Simulink Toolstrip.
