DPI Generation for Simulink Subsystem
You can use a DPI component generated from a Simulink subsystem in two ways :
Export SystemVerilog DPI Component — You can integrate this component into your HDL simulation as a behavioral model. The component generator supports test points and tunable parameters. You can also generate a SystemVerilog test bench that verifies the generated DPI component against data vectors from your subsystem. See Generate SystemVerilog DPI Component.
Generate SystemVerilog DPI Test Bench (with HDL Coder™) — Use this test bench to verify your generated HDL code using C code generated from your entire Simulink model, including the DUT and data sources. See Verify HDL Design Using SystemVerilog DPI Test Bench (HDL Coder).
To use this functionality, download and install the ASIC Testbench for HDL Verifier add-on. This feature also requires Simulink Coder™.
|HDL Verifier||Generate HDL verification artifacts and follow verification workflows from a Simulink subsystem (Since R2020b)|
|Assertion||Generate SystemVerilog assertions from Simulink assertion|
Generate and Verify a DPI Component
- DPI Component Generation with Simulink
If you have a Simulink Coder license, you can generate SystemVerilog DPI components using one of two methods.
- SystemVerilog DPI Test Benches
Choose between the two types of SVDPI test benches.
- Generate SystemVerilog DPI Component
Generate a DPI component from Simulink, and explore various configuration parameters.
- Use Generated DPI Functions in SystemVerilog
How to export the generated DPI component to a SystemVerilog environment.
- Verify Generated Component Against Simulink Data
Start ModelSim® or Questa® in GUI mode.
- Generate SystemVerilog Assertions from Simulink Test Bench
Generate SystemVerilog assertions from your Simulink environment.
Advanced DPI Options
- Generate Cross-Platform DPI Components
Generate a DPI component for an operating system different from your MATLAB® host machine.
- Customize Generated SystemVerilog Code
Describes how to customize the generated SystemVerilog code.
- Tune Gain Parameter During Simulation
Generate a DPI component that provides tunable access to a parameter.
- SystemVerilog DPI Component Test Point Access
You can designate internal signals in your model as test points and configure the SystemVerilog DPI generator to create one or more access functions.
- Generate SystemVerilog Assertions and Functional Coverage
Generate SystemVerilog immediate assertions from
verifystatements and model verification blocks, and collect functional coverage information (requires Simulink Test™ license).
Verify Generated HDL Code with SystemVerilog DPI Test Bench (requires HDL Coder license)
- Verify HDL Design Using SystemVerilog DPI Test Bench (HDL Coder)
This example shows how to use SystemVerilog DPI test bench for verification of HDL code where a large data set is required.
- Generate Test Bench and Enable Code Coverage Using the HDL Workflow Advisor (HDL Coder)
Generate test bench and code coverage for generated HDL code using the HDL Workflow Advisor.