Parallel Link Designer

Simulation Parameters control how the analysis is run in the Parallel Link Designer app. For detailed information about them, see Simulation Parameters Used in Parallel Link Design.

There are two types of corner conditions you can vary using the Parallel Link Designer app.

For more information, see Specify Corner Conditions in Parallel Link Design.

You can specify the stimulus patterns for the time domain analysis. If the specified pattern for a designator has fewer bits than the simulation length, the pattern is repeated from the first bit of the pattern. If the pattern is longer than the simulation length the simulation will end at the time specified by Time Domain Stop. For more information, see Stimulus Patterns in Parallel Link Design.

In Parallel Link Designer app, pre-layout crosstalk analysis is referred to as widebus crosstalk analysis. It consists of single transfer sheets (transfer nets) and a “widebus” or coupled sheet with a victim transfer net and one or more aggressor nets.

Each unique transfer net on a widebus schematic sheet is known as a “widebus group”. That group consists of ONLY the transfer net designators (drivers, receivers or I/O buffers). On a widebus sheet any widebus group can be a victim or aggressor and multiple instances of any widebus group can be placed on the schematic. The widebus groups inherit the designator properties defined in their transfer net sheet. Coupled w-lines, connectors, package models or s-parameter blocks can then be used in the widebus schematic to connect up each widebus group. One of the instances of a widebus group will be designated as the victim net on the schematic.

Widebus analysis can be performed on any project, even previous incarnations of a design. The following requirements are:

To create a widebus sheet there must be at least one transfer net included in the schematic set. Select File > Schematic Sheet > New Sheet from the app toolbar. In the newly opened New Sheet dialog box, select Widebus and select the widebus groups to be added to the sheet and the number of instances of each.

The Parallel Link Designer app supports the clock forwarding methodology defined in IBIS BIRD 204. This BIRD describes a mechanism by which the clock waveform, or recovered clock times, can be passed to the data AMI receiver model to allow the model maker access to the clock. This enables the receiver model to include clock phase noise, clock tree delays, phase interpolators, etc. IBIS BIRD204 has been approved by the IBIS committee and will be included in the IBIS 7.1.

A serial-link channel uses a CDR (clock data recovery) circuit in the receiver to create a clock signal that is then used to latch each individual data bit coming into the core of an IC. The IBIS-AMI standard was created to model this operation and a CDR is required to be present, either in the receiver model itself (the norm) or in the EDA tool that is running the simulation. By contrast, in a parallel-link channel no CDR is present. Instead, a separate clock (or strobe) signal is sent along with the data signals, which is used to latch sets of data bits at one time. This is known as clock-forwarding.

Clock forwarding is accessed by selection of a clock group in the Widebus Groups dialog box. The clock group identifies the clock and which respective data signals are associated with it. This relationship is used for analyzing clock recovery in the parallel interface.

Any widebus group transfer net that has been set up as a clock or strobe will be considered to be a clock group on the widebus sheet. The clock group drop down menu selection will show all strobe/clock groups on the current widebus sheet, plus "<none>". Clock transfer nets will default to “<none>”. Data transfer nets will default to first clock or strobe associated sheet. Each data group can be associated with a different clock group which also supports sweeping of victim group. For more information, see DDR5 IBIS-AMI with Clock Forwarding.