Bus to Vector

Convert virtual bus to vector

Libraries:
Simulink / Signal Attributes
HDL Coder / Signal Attributes

Description

The Bus to Vector block converts a virtual bus to a vector. Use the Bus to Vector block only to replace an implicit bus-to-vector conversion with an explicit conversion.

Blocks that do not accept buses may implicitly convert buses to vectors. When a bus is treated as a vector, bus elements become inaccessible. To identify and correct buses used as vectors, use the Model Advisor check Check bus signals treated as vectors or the function Simulink.BlockDiagram.addBusToVector.

Examples

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Explicitly Define Bus-To-Vector Conversions

Open Live Script

To more easily identify unexpected conversions, specify acceptable bus-to-vector conversions with Bus to Vector blocks.

Open and simulate the ex_bus_to_vector model.

model = "ex_bus_to_vector";
load_system(model);
sim(model);
open_system(model);

The model simulates correctly, but the input to the Gain block is a bus, while the output is a vector. The Gain block implicitly converts the bus to a vector.

To insert Bus to Vector blocks where blocks implicitly convert buses to vectors, use the Simulink.BlockDiagram.addBusToVector function with the third argument set to false.

When you use the Simulink.BlockDiagram.addBusToVector function with the third argument set to false, the function saves the model. To create a copy of the ex_bus_to_vector model, this example uses the save_system function.

model1 = 'ex_bus_to_vector_blocks';
save_system(model,model1)

[blocks,busToVectors] = ...
    Simulink.BlockDiagram.addBusToVector(model1,true,false)

### Processing block diagram 'ex_bus_to_vector_blocks'
### Number of blocks left that are connected to a bus being used as a vector: 2
### Successfully inserted Bus to Vector Blocks in model. Preparing to save model and/or libraries
### To eliminate modeling errors in the future, please enable strict bus modeling by setting the 'Bus signal treated as vector' diagnostic in the Configuration parameter dialog, Diagnostic/Connectivity tab to 'error'
### Done processing block diagram 'ex_bus_to_vector_blocks'

blocks=1×2 struct array with fields:
    BlockPath
    InputPort
    LibPath

busToVectors = 2x1 cell
    {'ex_bus_to_vector_blocks/Bus to Vector' }
    {'ex_bus_to_vector_blocks/Bus to Vector1'}

The Gain blocks no longer implicitly convert the buses to vectors. The inserted Bus to Vector blocks perform the conversions explicitly.

Ports

Input

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Port_1 — Bus to convert to vector
scalar | vector | bus

An input bus must consist of scalars or 1-D, row, or column vectors that have the same data type, signal type, and sampling mode. If the input is a nonbus signal, the block does no conversion.

Output

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Port_1 — Output vector
vector

The dimensions of the output vector depend on the dimensions of the input bus elements. If the input bus contains row or column vectors, the block output is a row or column vector, respectively. Otherwise, the output is a 1-D vector.

Block Characteristics

Data Types	`Boolean` \| `bus` \| `double` \| `enumerated` \| `fixed point` \| `half` \| `integer` \| `single`
Direct Feedthrough	`no`
Multidimensional Signals	`no`
Variable-Size Signals	`no`
Zero-Crossing Detection	`no`

Tips

To identify buses treated as vectors during simulation, set the Bus signal treated as vector configuration parameter to warning or error. The default setting for Bus signal treated as vector is none, which generates no warning or error message when a block implicitly converts a bus to a vector.
If you use Save As to save a model to a Simulink^® version before R2007a, a null subsystem that outputs nothing replaces each Bus to Vector block. Before you can use the model, reconnect or otherwise correct each path that used to contain a Bus to Vector block but now is interrupted by a null subsystem.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Actual data type or capability support depends on block implementation.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

To learn more about using buses for HDL code generation, see Buses (HDL Coder) and Use Buses to Improve Readability of Model and Generate HDL Code (HDL Coder).

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Actual data type or capability support depends on block implementation.

Version History

Introduced in R2007a

Bus to Vector

Description

Examples

Explicitly Define Bus-To-Vector Conversions

Ports

Input

Port_1 — Bus to convert to vector
scalar | vector | bus

Output

Port_1 — Output vector
vector

Block Characteristics

Tips

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

See Also

Blocks

Checks

Functions

Topics

Bus to Vector

Description

Examples

Explicitly Define Bus-To-Vector Conversions

Ports

Input

Port_1 — Bus to convert to vector scalar | vector | bus

Output

Port_1 — Output vector vector

Block Characteristics

Tips

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

See Also

Blocks

Checks

Functions

Topics

Port_1 — Bus to convert to vector
scalar | vector | bus

Port_1 — Output vector
vector

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.