合成接口

对信号或消息进行组合以降低组件接口处的模型复杂度

为了降低模型的复杂度，可以使用总线将单个信号或消息组合为合成线。

虚拟总线可满足合成接口的大多数建模要求，并可灵活地对不同类型的信号进行组合。

有关建模方法的比较，请参阅合成接口规范。

模块

In Bus Element	Select input from external port
Out Bus Element	Specify output of external port

Bus to Vector	将虚拟总线转换为向量
Signal Conversion	将信号转换为新类型，而不改变信号值

Simulink.Bus.addElementToPort Add element to input bus element port (自 R2022b 起)

`getNumLeafBusElements`	Number of leaf elements in `Simulink.Bus` object
`getLeafBusElements`	Leaf elements in `Simulink.Bus` object
`Simulink.Bus`	指定总线的属性
`Simulink.BusElement`	指定总线元素的属性
`Simulink.Bus.cellToObject`	Create `Simulink.Bus` objects from cell array of bus information
`Simulink.Bus.createObject`	从模块或 MATLAB 结构体创建 `Simulink.Bus` 对象
`Simulink.Bus.objectToCell`	Create cell array of bus information from `Simulink.Bus` objects
`Simulink.Bus.save`	Save `Simulink.Bus` object definitions in function

Simulink.Bus.createMATLABStruct 创建与总线使用相同的层次结构和属性的 MATLAB 结构体

Simulink.BlockDiagram.addBusToVector Convert virtual bus signals into vector signals by adding Bus to Vector blocks

组件接口视图	Display component interfaces to trace port connections and author ports
信号层次结构查看器	View signal hierarchy and trace signal to source or destination
类型编辑器	Create, modify, and manage types, such as bus objects

根 Outport 模块上未指定总线对象	Diagnostic action to take when root Outport block of referenced model does not specify bus object for bus output
元素名称不匹配	总线元素名称与对应的总线元素对象名称不匹配时要执行的诊断操作
总线信号视为向量	Diagnostic action to take when virtual bus is treated as vector
非总线信号被视为总线信号	Diagnostic action to take when nonbus signals are treated as buses
修复总线选择	Diagnostic action to take when upstream bus hierarchy changes break selections

合成接口规范

组合信号、消息或连接以简化模型外观。
- 步骤 1: Explore Composite Interfaces
- 步骤 2: Compare Capabilities of Composite Interfaces
Bus-Capable Blocks
Identify the blocks that support virtual buses, nonvirtual buses, and arrays of buses.

将信号或消息组合到虚拟总线中
创建总线以减少模块图中的信号线数量。
Simplify Subsystem and Model Interfaces with Bus Element Ports
Group multiple lines into a bus at the input or output of a model component.
Display Bus Information
Display information about buses, such as signal hierarchy and whether the bus is virtual or nonvirtual.
Identify Automatic Bus Conversions
Recognize modeling patterns that cause hidden Bus To Vector and Signal Conversion blocks.
Programmatically Create Bus Element Ports
Add blocks for bus element ports and specify element attributes using MATLAB^® functions.

Modify Bus Hierarchy
Change the order and hierarchy of nested buses and their elements.
将信号值赋给总线元素
使用 Bus Assignment 模块替换分配给总线元素的信号。
Specify Initial Conditions for Bus Elements
Specify bus element values as initial conditions for buses.
Share and Reuse Bus-Routing Blocks
Share blocks that create or interact with buses using subsystem references or custom libraries.

Create Nonvirtual Buses
Create buses that appear in generated code and support modeling constructs such as arrays of buses.
Modify Sample Times for Nonvirtual Buses
Make the sample time of signals the same so that you can group them in a nonvirtual bus.
Generate Code for Nonvirtual Buses
Use a structure in code generation to represent a nonvirtual bus. Control data types of initial condition structure fields.
Inspect Generated Code for Nonvirtual Buses
Find nonvirtual buses in generated code for a simple model.

使用总线数组组合非虚拟总线
通过将具有相同数据类型的非虚拟总线合并为一个数组来简化模型以进行迭代处理。
使用总线数组
设置模型以使用总线数组来选择信号、为信号赋值、执行迭代处理、记录和加载信号以及初始化信号。
Iteratively Process Nonvirtual Buses with Arrays of Buses
Update a model to use arrays of buses to apply the same algorithm to multiple nonvirtual buses with the same data type.