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FMCOMMS5 Transmitter

Send data to FMCOMMS5 Zynq radio hardware

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Add-On Required: This feature requires the SoC Blockset Support Package for AMD FPGA and SoC Devices add-on.

  • FMCOMMS5 Transmitter block

Libraries:
SoC Blockset Support Package for AMD FPGA and SoC Devices / Zynq-7000 / ZC706

Description

The FMCOMMS5 Transmitter block sends data to an FMCOMMS5 Zynq® radio hardware. The block supports the Xilinx® ZC706 radio hardware with Analog Devices® FMCOMMS5 RF card.

You can use the FMCOMMS5 Transmitter block to simulate and develop various software-defined radio (SDR) applications. This diagram shows the conceptual overview of transmitting and receiving radio signals in Simulink® using the SoC Blockset™ Support Package for AMD FPGA and SoC Devices. Simulink interacts with the FMCOMMS5 Transmitter block to send data to the radio hardware.

For transmitting a radio signal over the air, pass the signal generated in Simulink to a transmitter block. The transmitter block forwards the signal to the radio hardware. For receiving a radio signal over the air, use a receiver block. The receiver block forwards the signal received from the radio hardware for post processing in Simulink.

Examples

Transmit Data on Multiple Channels Using Simulink Block

Transmit Data on Multiple Channels Using Simulink Block

This model is set up to transmit data on two channels. The Channel mapping parameter of the E3xx Transmitter block is set to [1 2]. The underflow port is disabled by clearing the Enable output port for underflow indicator parameter. The Sine Wave Channel 1 block is configured to generate an 8 kHz sine wave. The Sine Wave Channel 2 block is configured to generate a 1 kHz sine wave. Both sine waves are sampled at 1 MHz. When you run this model, the E3xx Transmitter block sends the generated and combined sine waves through the air. You can inspect the generated data in the Spectrum Analyzer blocks.

Limitations

  • To use this block, in the hardware setup, set Hardware Board to Xilinx Zynq ZC706 evaluation kit and Add-on Card to FMCOMMS5.

  • Use the IP core workflow to generate HDL code. This block does not support using the SoC Builder tool. For more information on workflows, see SoC Generation Workflows.

Ports

Input

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Input signal sent to the radio hardware, specified as a complex matrix. The number of columns in the matrix depends on the number of channels in use, as specified by the Channel mapping parameter. Each column corresponds to a channel of complex data sent via one channel. In single-channel mode, the number of elements in a column must be even.

This port supports complex values with these data types:

  • 16-bit signed integers — Since the AD9361 RF chip has a 12-bit DAC, only the 12 most significant bits of the I and Q samples are used.

  • Single-precision floating point — Complex values in the range of [–1, 1]. Since the AD9361 RF chip has a 12-bit DAC, numbers of magnitude less than 0.0625 are lost.

  • Double-precision floating point — Complex values in the range of [–1, 1]. Since the AD9361 RF chip has a 12-bit DAC, numbers of magnitude less than 0.0625 are lost.

To determine whether data has been transmitted successfully, enable the underflow port.

Dependencies

To enable this port, set the Data source select parameter to Input port.

Data Types: int16 | single | double
Complex Number Support: Yes

External RF center frequency, specified as a nonnegative finite scalar. The valid center frequency range is from 70 MHz to 6 GHz.

Dependencies

To enable this port, set the Source of center frequency parameter to Input port.

Data Types: double

External gain source, specified as a numeric scalar, or a 1-by-2 or 1-by-4 numeric vector. The valid gain range is –89.75 dB to 0 dB. The resolution is 0.25 dB.

Set the gain based on the Channel mapping parameter configuration.

  • For a single channel, specify the gain as a scalar.

  • For two or four channels that use the same gain value, specify the gain as a scalar. The block applies the gain by scalar expansion.

  • For two or four channels that use different gain values, specify the gain as a 1-by-2 or 1-by-4 vector, respectively. The ith element of the vector is applied to the ith channel specified by the Channel mapping parameter.

Dependencies

To enable this port, set the Source of gain parameter to Input port.

Data Types: double

Output

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Data discontinuity flag, returned as one of these values:

  • 1 indicates the presence of underflow resulting in noncontiguous data.

  • 0 indicates no underflow.

You can use this value as a diagnostic tool to determine real-time operation of the FMCOMMS5 Transmitter block. If your model is not running in real time, increase the frame size to approach or achieve real-time performance. Alternatively, you can decrease the baseband sampling rate.

Note

Running the block for the first time initializes the radio. Because this initialization can result in an underflow, ignore the underflow output port value of the first run.

Dependencies

To enable this port, on the Main tab, select the Enable output port for underflow indicator parameter.

Data Types: Boolean

Parameters

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The FMCOMMS5 Transmitter block supports up to four channels to send data to the FMCOMMS5 Zynq radio hardware. Use the Channel mapping parameter to indicate whether to use a single channel or multiple channels. For each channel in the input signal, data, you can set the Gain (dB) parameter independently, or you can apply the same setting to all channels. If you select direct digital synthesis (DDS) transmission for the Data source select parameter, you can also set all DDS-based parameters independently. All other parameter values are applied to each channel in use.

To check connectivity between the block and the radio hardware, and to synchronize radio settings between them, on the Main tab, click Info.

When you set block parameter values, the FMCOMMS5 Transmitter block first checks that the values have the correct data types. If the values pass those checks, the values can still be out of range for the radio hardware. In that case, the radio hardware sets the actual value as close to the specified value as possible. When you next synchronize the block with the radio hardware by clicking Info, a dialog box displays the actual values.

If a parameter is listed as tunable, then you can change its value during simulation.

Main Tab

IP address of the radio hardware, specified as a dotted-quad expression.

This parameter must match the physical IP address of the radio hardware assigned during hardware setup. For more information, see Set Up Xilinx Devices. If you configure the radio hardware with an IP address other than the default, update Radio IP address accordingly.

Source of center frequency, specified as one of these options:

  • Dialog — Set the center frequency by using the Center frequency (Hz) parameter.

  • Input port — Set the center frequency by using the center frequency input port.

RF center frequency in Hz, specified as a nonnegative scalar. The valid range for center frequency is 70 MHz to 6 GHz.

Tunable: Yes

Dependencies

To enable this parameter, set the Source of center frequency parameter to Dialog.

Data Types: double

  • Dialog — Specify the gain by using the Gain (dB) parameter.

  • Input port — Specify the gain by using the gain input port.

Gain in dB, specified as a numeric scalar, or a 1-by-2 or 1-by-4 numeric vector. The valid gain range is –89.75 dB to 0 dB. The resolution is 0.25 dB.

Set the gain based on the Channel mapping parameter configuration.

  • For a single channel, specify the gain as a scalar.

  • For two or four channels that use the same gain value, specify the gain as a scalar. The block applies the gain by scalar expansion.

  • For two or four channels that use different gain values, specify the gain as a 1-by-2 or 1-by-4 vector, respectively. The ith element of the vector is applied to the ith channel specified by the Channel mapping parameter.

Tunable: Yes

Dependencies

To enable this parameter, set the Source of gain parameter to Dialog.

Data Types: double

Channel input mapping, specified as one of these values:

  • Integer from 1 to 4 — The integer value indicates which single channel is in use.

  • [N M], where N and M are distinct integers from 1 to 4 — Channels N and M are in use.

  • [1 2 3 4] — All four channels are in use.

The RF chip of the radio hardware determines the number of channels you can use for sending data. For the FMCOMMS5, two AD9361 RF chips are used to provide support for four channels. The channels specified by 1 and 2 are situated on the first AD9361 chip. The channels specified by 3 and 4 are situated on the second AD9361 chip. Using multiple channels across the two chips has certain limitations. For more information, see Multiple Channel Synchronization for FMCOMMS5.

Supported Radio HardwareRF ChipNumber of ChannelsSupported RF Ports

ZC706 and FMCOMMS5

2 x AD93614

  • For AD9361 Chip A: TX1A_A, RX1A_A, TX2A_A, RX2A_A

  • For AD9361 Chip B: TX1A_B, RX1A_B, TX2A_B, RX2A_B

Baseband sampling rate in Hz, specified as a positive scalar. The valid range of this parameter is 520.834 kHz to 61.44 MHz.

Note

To synchronize the block with the radio hardware, on the Menu tab, click Info. If the specified and actual rates have a small mismatch, verify that the computed rate is close to the value you actually want.

Data Types: double

Select this parameter to enable the underflow output port during host-radio hardware data transfers.

Filter Tab

When you select this parameter, the filter chain uses a custom filter design instead of the default filter design. For example, if the gain or bandwidth characteristics of the default filter does not satisfy the requirements for your application, you can design a custom filter that meets your specific requirements. If the FMCOMMS5 Transmitter block does not have a custom filter design applied yet, click on Launch filter wizard to open the ADI filter wizard. The wizard enables you to design a custom filter for the Analog Devices AD9361 RF chips based on the Baseband sample rate (Hz) parameter. You can adjust and optimize the settings for calculating the analog filters, interpolation and decimation filters, and FIR coefficients. When you finish with the wizard, to apply the custom filter design to the block, click Apply on the block mask. The setting is applied to each channel in use across both AD9361 chips.

Note

When applying a custom filter to the FMCOMMS5 Transmitter block by using the ADI filter wizard, Use custom filter is automatically selected. To switch between the default and your custom filter design, clear or select Use custom filter, respectively. Then click Apply on the block mask.

For more information, see Baseband Sampling Rate and Filter Chains.

Advanced Tab

Select this parameter to enable the radio hardware data path to bypass the algorithm generated and programmed during FPGA targeting or hardware-software co-design. For more information, see FPGA Targeting Workflow and Hardware-Software Co-Design Workflow.

Source of data, specified as one of these values:

  • Input Port — This selection enables the data input port.

  • DDS — This selection enables DDS transmission. The block uses two additive tones for each channel. To set the tone frequency and tone scale of these tones, use the Tone 1 Frequency (Hz), Tone 2 Frequency (Hz), Tone 1 Scale [0-1], and Tone 2 Scale [0-1] parameters. The DDS signals are generated on the FPGA.

First DDS tone frequency in Hz, specified as one of these options:

  • Numeric scalar — Use this option for a single channel or to specify the same frequency for all channels in use. The object applies scalar expansion for each channel specified by the Channel mapping parameter.

  • 1-by-2 or 1-by-4 numeric vector — Use this option to specify different frequencies for two or four channels, respectively. The ith element of the vector is applied to the ith channel specified by the Channel mapping parameter.

The valid range of Tone 1 Frequency (Hz) is from 0 to Baseband sample rate (Hz) / 2.

Dependencies

To enable this parameter, set the Data source select parameter to DDS.

Data Types: double

Second DDS tone frequency in Hz, specified as one of these options:

  • Numeric scalar — Use this option for a single channel or to specify the same frequency for all channels in use. The object applies scalar expansion for each channel specified by the Channel mapping parameter.

  • 1-by-2 or 1-by-4 numeric vector — Use this option to specify different frequencies for two or four channels, respectively. The ith element of the vector is applied to the ith channel specified by the Channel mapping parameter.

The valid range of Tone 2 Frequency (Hz) is from 0 to Baseband sample rate (Hz) / 2.

Dependencies

To enable this parameter, set the Data source select parameter to DDS.

Data Types: double

First DDS tone scale in millionths of full scale, specified as one of these options:

  • Numeric scalar — Use this option for a single channel or to specify the same scale for all channels in use. The object applies scalar expansion for each channel specified by the Channel mapping parameter.

  • 1-by-2 or 1-by-4 numeric vector — Use this option to specify different scales for two or four channels, respectively. The ith element of the vector is applied to the ith channel specified by the Channel mapping parameter.

The valid range of Tone 1 Scale [0-1] is from 0 to 1.

Dependencies

To enable this parameter, set the Data source select parameter to DDS.

Data Types: double

Second DDS tone scale in millionths of full scale, specified as one of these options:

  • Numeric scalar — Use this option for a single channel or to specify the same scale for all channels in use. The object applies scalar expansion for each channel specified by the Channel mapping parameter.

  • 1-by-2 or 1-by-4 numeric vector — Use this option to specify different scales for two or four channels, respectively. The ith element of the vector is applied to the ith channel specified by the Channel mapping parameter.

The valid range of Tone 2 Scale [0-1] is from 0 to 1.

Dependencies

To enable this parameter, set the Data source select parameter to DDS.

Data Types: double

Timeout for I/O operations in seconds, specified as one of these options:

  • Inf — The block waits indefinitely to complete I/O operations.

  • Nonnegative scalar, N — The block waits N seconds to complete I/O operations. Zero seconds corresponds to a non-blocking setup.

Data Types: double

Built-in self-test loopback mode, specified as one of these options:

  • Disabled — Disable BIST loopback.

  • Digital Tx -> Digital Rx — Enable digital signals to loop back within the device. The signals bypass the RF stage.

  • RF Rx -> RF Tx — Enable incoming receiver RF signals to loop back to the RF transmitter port. The signals bypass the FPGA.

BIST signal injection mode, specified as one of these values:

  • Disabled — Disable BIST signal injection.

  • Tone Inject Tx — Enable BIST signal injection to transmit path.

  • Tone Inject Rx — Enable BIST signal injection to receive path.

When you enable BIST signal injection, you can set the source of BIST signal generation with the Signal generator mode parameter.

Source of BIST signal generation, specified as one of these options:

  • PRBS — Use the pseudo random binary sequence (PRBS) generator of the board.

  • Tone — Use the tone generator of the board. To set the tone frequency and tone level, use the Tone frequency (Hz) and Tone level (dB) parameters, respectively.

Dependencies

To enable this parameter, set the Test signal injection parameter to Tone Inject Tx or Tone Inject Rx.

BIST tone frequency, specified as Fs/32, Fs/16, Fs*3/32, or Fs/8.

Dependencies

To enable this parameter, set the Signal generator mode parameter to Tone.

BIST tone level, specified as 0, -6, -12, or -18.

Dependencies

To enable this parameter, set the Signal generator mode parameter to Tone.

Version History

Introduced in R2019a

See Also

Objects

Blocks

Topics

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