Wireless Communication

Implement applications for wireless communications using SoC Blockset

You can use SoC Blockset™ to model and simulate wireless communication applications for 5G, WLAN, and LTE. Simulate your algorithm with SoC components such as DDR memory, software tasks, RF data conversion, and AXI interfaces. You can then take additional steps to deploy your design on an SoC device.

Featured Examples

Receive Signal Waveform Using DDR4 on Xilinx RFSoC Device

Design, simulate, and deploy a system to write and read the captured RF samples from external double data rate 4 (DDR4) memory in Simulink® with an SoC Blockset® implementation targeted on the Xilinx® Zynq® UltraScale+™ RFSoC ZCU111 evaluation kit. In this example, you can write the captured samples of an analog-to-digital converter (ADC) into external programmable logic (PL) DDR4 memory, read the samples from the PL DDR4 memory, and send them to the processor to display. A tone signal is generated in FPGA using a numerically controlled oscillator (NCO) to verify the receive path.

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Frequency Hopping Using Xilinx RFSoC Device

Design and implement frequency hopping algorithm using Xilinx^® RF Data Converter numerically controlled oscillator (NCO) real time ports.

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QPSK Transmit and Receive Using Zynq and FMCOMMS2/3/4

Simulate and deploy quadrature phase-shift keying (QPSK) transmit and receive algorithm using SoC Blockset.

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OFDM Transmit and Receive Using AMD RFSoC Device

Simulate and deploy OFDM transmit and receive algorithm using SoC Blockset on Xilinx RFSoC device.

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Introduction to 5G NR Signal Detection using AMD RFSoC

Deploy primary synchronization signal (PSS) correlation and synchronization signal block (SSB) demodulation using SoC Blockset on Xilinx RFSoC device.

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5G NR SIB1 Recovery for FR1 and FR2 Using AMD RFSoC Device

Deploy 5G NR SIB1 recovery algorithm for FR1 and FR2 using SoC Blockset on Xilinx RFSoC device.

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5G NR Downlink Signal Measurements Using AMD RFSoC Device

Measure SSB signal quality and error vector magnitude (EVM) of the received resource grid using SoC Blockset on Xilinx RFSoC device.

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DVB-S2 HDL PL Header Recovery Using Analog Devices AD9361/AD9364

Deploy Digital Video Broadcasting Satellite Second Generation (DVB-S2) time, frequency, and phase synchronization and PL header recovery algorithm using SoC Blockset.

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DVB-S2 Receive Using AMD RFSoC Device

Simulate and deploy DVB-S2 transmit and receive algorithm using SoC Blockset on Xilinx RFSoC device.

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WLAN Receiver Using AMD RFSoC Device

Simulate and deploy WLAN transmit and receive algorithm using SoC Blockset on Xilinx RFSoC device.

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Packet-Based ADS-B Transceiver

Packet-based systems are common in wireless communications. Data is received over the air and is decoded as discrete packet data on a compute device. For given system requirements, it is difficult to design a system and implement directly on SoC as it often involves long iterations of debugging and integration on hardware since hardware effects are difficult to account for at design time. In this example, you will design packet-based airplane tracking application based on Automatic Dependent Surveillance Broadcast (ADS-B) standard, partitioned between FPGA and embedded processor. Unlike traditional methods, you will simulate the application design with memory interface before implementation on hardware using SoC Blockset™ to shorten development time. You will then validate the design on hardware by automatically generated code from the model.

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