C28x Hardware Interrupt

Interrupt Service Routine to handle hardware interrupt on C28x processors

Libraries:
C2000 Microcontroller Blockset / Scheduling

Description

Execution scheduling models based on timer interrupts do not meet the requirements of some real-time applications to respond to external events. The C28x Hardware Interrupt block addresses this problem by allowing asynchronous processing of interrupts triggered by events managed by other blocks in the C28x DSP Chip Support Library.

When the C28x Hardware Interrupt block has an external interrupt selection, the selection enables interrupts on the selected general-purpose I/O pins. To configure these pins, see the Configuration Parameters > Hardware Implementation > Hardware board settings > Target hardware resources > External Interrupt pane. For more information, see Model Configuration Parameters for Texas Instruments C2000 Processors.

The task priority indicates the relative importance of the tasks associated with the asynchronous interrupts. The lowest value in this field represents the highest priority. The default priority value of the base rate task is 40, so the priority value for each asynchronously triggered task must be less than 40 (to configure them as higher-priority) for these tasks to preempt the base rate task.

The preemption flag determines whether a given interrupt is preemptable or not. Preemption overrides prioritization, if an interrupt triggers a higher-priority task while a lower-priority task is running, the execution of the lower-priority task can be suspended and resumed after the completion of the higher priority task, provided the lower-priority task is configured as preemptable.

Vectorized Output

The output of this block is a function call. The size of the function call line equals the number of interrupts the block is set to handle. Each interrupt is represented by four parameters shown on the dialog box of the block. These parameters are a set of four vectors of equal length. Each interrupt is represented by one element from each parameter (four elements total), one from the same position in each of these vectors.

Each interrupt is described by:

CPU interrupt numbers
Peripheral Interrupts Expansion (PIE) interrupt numbers
Task priorities
Preemption flags

Examples

Synchronizing ePWM and eCAP Modules using Time-Base Counter Synchronization

Use time-base counter synchronization in C2000™ Microcontroller Blockset.

Open Model

ADC-PWM Synchronization Using ADC Interrupt

Use the ADC block to sample an analog voltage and use the PWM block to generate a pulse waveform. This example also shows how to use the Hardware Interrupt block to synchronize the change in the PWM duty cycle with analog to digital conversion of voltage. In the generated code, changes in the voltage of the ADC input alter the duty cycle of the PWM output. The period of the PWM waveform remains constant.

Open Model

Asynchronous Scheduling

Use the Texas Instruments™ C28x™ peripherals and Hardware Interrupt blocks to control the real-time execution of Simulink® function-call subsystems in an asynchronous fashion.

Open Model

Field-Oriented Control of PMSM with Quadrature Encoder Using C2000 Processors

Implements the field-oriented control (FOC) technique to control the speed of a three-phase permanent magnet synchronous motor (PMSM). The FOC algorithm requires rotor position feedback, which is obtained by a quadrature encoder sensor. For details about FOC, see Field-Oriented Control (FOC) (Motor Control Blockset).

Open Model

Schedule a Multi-Rate Controller for a Permanent Magnet Synchronous Machine

Create a real-time executable for a Texas Instruments™ F28335 embedded target. You will build upon the algorithm specified in the example Field-Oriented Control of Permanent Magnet Synchronous Machine (Embedded Coder) by adding timing and peripheral specifications. You will learn an advanced technique to schedule the algorithm based on the periodic end-of-conversion event of the ADC.

Open Model

Photovoltaic Inverter with MPPT Using Solar Explorer Kit

Implement a photovoltaic (PV) inverter system using the C2000™ Microcontroller Blockset. The example uses the Texas Instruments Solar Explorer Kit along with the Texas Instruments F28035 controlCARD.

Open Model

Ports

Input

expand all

SimIRQ — Simulation interrupt input port
scalar

The interrupt block initiates a function call in simulation when you enable the SimIRQ input port. However, SimIRQ is ignored in the generated code.

Dependencies

To enable the SimIRQ port, select the Enable simulation port parameter.

Data Types: Boolean

Output

expand all

IRQ — Generate interrupt request
`Scalar`

The output of this block is a function call. The size of the function call line equals the number of interrupts the block is set to handle.

Parameters

expand all

CPU interrupt number — Specify vector of CPU interrupt
`[1 1]` (default) | integer in [1, 8]

Enter a vector of CPU interrupt numbers for the interrupts you want to process asynchronously.

PIE interrupt number — Specify a vector of PIE interrupt
`[1 2]` (default)

Enter a vector of PIE interrupt numbers for the interrupts you want to process asynchronously.

Simulink task priorities — Provides relative importance of tasks associated with the asynchronous interrupts
`[30 26]` (default)

Enter a vector of task priorities for the interrupts you want to process asynchronously.

Preemption flags: preemptable-1, non-preemptable-0 — Specify a vector of preemption flags for the interrupts
`0 0` (default)

Enter a vector of preemption flags for the interrupts you want to process asynchronously.

Enable simulation input — Enable simulation ports to block
`off` (default) | `on`

Select this parameter to add an compatible simulation input port.

Selecting this parameter enables you to test asynchronous interrupt processing in the context of your Simulink^® software model.

PIE and CPU interrupt numbers

Each interrupt is described by a CPU interrupt number, a PIE interrupt number, a task priority, and a preemption flag.

The CPU and PIE interrupt numbers together uniquely specify a single interrupt for a single peripheral or peripheral module.

The PIE and CPU interrupt numbers for the c28x processors F280013x and F280015x that support 12×8 interrupts are:

PIE and CPU Interrupt Numbers for F280013x and F280015x Processors

PIE ⇒	1	2	3	4	5	6	7	8
CPU ⇓	1	2	3	4	5	6	7	8
1	ADCA1	ADCC1	-	XINT1	XINT2	SYS_ERR	TIMER0	WAKE
2	EPWM1_TZ	EPWM2_TZ	EPWM3_TZ	EPWM4_TZ	EPWM5_TZ	EPWM6_ TZ	EPWM7_TZ
3	EPWM1	EPWM2	EPWM3	EPWM4	EPWM5	EPWM6	EPWM7
4	ECAP1	ECAP2	-	-	-	-	-
5	EQEP1	-	-	-	-	-	-
6	SPIA_RX	SPIA_TX	-	-	-	-	DCC0
7	-	-	-	-	-	-	-	-
8	I2CA	I2CA_FIFO	I2CB	I2CB_FIFO	SCIC_RX	SCIC_TX	-	-
9	SCIA_RX	SCIA_TX	SCIB_RX	SCIB_TX	CANA_0	CANA_1	-	-
10	ADCA_EVT	ADCA2	ADCA3	ADCA4	ADCC_EVT	ADCC2	ADCC3	ADCC4
11	-	-	-	-	-	-	-	-
12	XINT3	XINT4	XINT5	-	FLSS_INT	-	-	-

The PIE and CPU interrupt numbers for the TI processor F28P65x that support 12×16 interrupts are:

PIE and CPU Interrupt Numbers for F28P65x Processors

PIE ⇒	1	2	3	4	5	6	7	8
CPU ⇓	1	2	3	4	5	6	7	8
1	ADCA1	ADCB1	ADCC1	XINT1	XINT2	-	TIMER 0	WAKE / WDOG
2	EPWM1_TZ	EPWM2_TZ	EPWM3_TZ	EPWM4_TZ	EPWM5_TZ	EPWM6_ TZ	EPWM7_TZ	EPWM8_TZ
3	EPWM1	EPWM2	EPWM3	EPWM4	EPWM5	EPWM6	EPWM7	EPWM8
4	ECAP1	ECAP2	ECAP3	ECAP4	ECAP5	ECAP6	ECAP7	Reserved
5	EQEP1	EQEP2	EQEP3	EQEP4	CLB1	CLB2	CLB3	CLB4
6	SPIA_RX	SPIA_TX	SPIB_RX	SPIB_TX	LINA_0	LINA_1	LINB_0	LINB_1
7	DMA_CH1	DMA_CH2	DMA_CH3	DMA_CH4	DMA_CH5	DMA_CH6	EQEP_5	EQEP_6
8	I2CA	I2CA_FIFO	I2CB	I2CB_FIFO	UARTA_INT	UARTB_INT	EPWM17_TZ	EPWM18_TZ
9	SCIA_RX	SCIA_TX	SCIB_RX	SCIB_TX	DCANA_1	DCANA_2	EPWM17	EPWM18
10	ADCA_EVT	ADCA2	ADCA3	ADCA4	ADCB_EVT	ADCB2	ADCB3	ADCB4
11	CPU1_CLA1_1	CPU1_CLA1_2	CPU1_CLA1_3	CPU1_CLA1_4	CPU1_CLA1_5	CPU1_CLA1_6	CPU1_CLA1_7	CPU1_CLA1_8
12	XINT3	XINT4	XINT5	CPU1_MPOST_INT	FLSS_INT	-	FPU_OVERFLOW	FPU_UNDERFLOW

PIE ⇒	9	10	11	12	13	14	15	16
CPU ⇓	9	10	11	12	13	14	15	16
1	I2CA	SYS_ERR	ECATSYNC0	ECATINTn	CIPC0	CIPC1	CIPC2	CIPC3
2	EPWM9_TZ	EPWM10_ TZ	EPWM11_TZ	EPWM12_TZ	EPWM13_TZ	EPWM14_TZ	EPWM15_TZ	EPWM16_TZ
3	EPWM9	EPWM10	EPWM11	EPWM12	EPWM13	EPWM14	EPWM15	EPWM16
4	FSITXA_INT1	FSITXA_INT2	FSITXB_INT1	FSITXB_INT2	FSIRXA_INT1	FSIRXA_INT2	FSIRXB_INT1	FSIRXB_INT2
5	SDFM1	SDFM2	ECATRST	ECATSYNC1	SDFM1DR1	SDFM1DR2	SDFM1DR3	SDFM1DR4
6	SPIC_RX	SPIC_TX	SPID_RX	SPID_TX	SDFM2DR1	SDFM2DR2	SDFM2DR3	SDFM2DR4
7	FSITXA_INT1	FSITXA_INT2	FSIRXA_INT1	FSIRXA_INT2	SDFM3DR1	SDFM3DR2	SDFM3DR3	SDFM3DR4
8	-	-	SDFM3	SDFM4	CLB5	CLB6	-	-
9	MCANSS_A0	MCANSS_A1	MCANSS_ECC_CORR_PLS	MCANSS_WAKE_AND_TS_PLS	PMBUSA	AES_INT	USBA	Reserved
10	ADCC_EVT	ADCC2	ADCC3	ADCC4	Reserved	Reserved	Reserved	ADCHECKINT
11	MCANSS_B0	MCANSS_B1	MCANSS_BECC_CORR_PLS	MCANSS_B_WAKE_AND_TS_PLS	SDFM4DR1	SDFM4DR2	SDFM4DR3	SDFM4DR4
12	_	ECAP6_INT2	ECAP7_INT2	-	CPU1_CRC_INT	CPU1_CLA1CRC_INT	CPU1_CLA OVER FLOW	CPU1_CLA UNDERFLOW

The following table lists the PIE and CPU interrupt numbers for the c28x processors F280x, F2802x, F2803x, F2805x, F2806x, F2833x, F28M35x, and F28M36x that support 12×8 interrupts. The row headers 1–12 represent the CPU values, and the column headers 1–8 represent the PIE values.

PIE and CPU Interrupt Numbers for F280x, F2802x, F2803x, F2805x, F2806x, F2833x, F28M35x, and F28M36x Processors

PIE ⇒	1	2	3	4	5	6	7	8
CPU ⇓	1	2	3	4	5	6	7	8
1	SEQ1INT (ADC) / ADCINT1	SEQ2INT (ADC) / ADCINT2	Reserved	XINT1	XINT2	ADCINT / ADCINT9	TINT0 (TIMER 0)	WAKEINT (LPM/WD)
2	EPWM1_TZINT	EPWM2_TZINT	EPWM3_TZINT	EPWM4_TZINT	EPWM5_TZINT	EPWM6_ TZINT	EPWM7_TZINT	EPWM8_TZINT
3	EPWM1_INT	EPWM2_INT	EPWM3_INT	EPWM4_INT	EPWM5_INT	EPWM6_ INT	EPWM7_INT	EPWM8_INT
4	ECAP1_INT	ECAP2_INT	ECAP3_INT	ECAP4_INT	ECAP5_INT	ECAP6_INT	EPWM10_TZINT / HRCAP1_INT	EPWM9_TZINT / HRCAP2_INT
5	EQEP1_INT	EQEP2_INT	EQEP3_INT	HRCAP3_INT	HRCAP4_INT	Reserved	EPWM10_INT	EPWM9_INT
6	SPIRXINTA (SPI-A)	SPITXINTA (SPI-A)	SPIRXINTB (SPIB_RX) / MRINTB (McBSP-B)	SPITXINTB (SPIB_TX) / MXINTB (McBSP-B)	SPIRXINTC (SPI-C) / MRINTA (McBSP-A_RX)	SPITXINTC (SPI-C) / MXINTA (McBSP-A_TX)	SPIRXINTD (SPI-D) / EPWM12_TZINT	SPITXINTD (SPI-D) / EPWM11_TZINT
7	DINTCH1 (DMA1)	DINTCH2 (DMA2)	DINTCH3 (DMA3)	DINTCH4 (DMA4)	DINTCH5 (DMA5)	DINTCH6 (DMA6)	EPWM12_INT	EPWM11_INT
8	I2CINT1A	I2CINT2A	Reserved	Reserved	SCIRXINTC (SCI-C)	SCITXINTC (SCI-C)	Reserved	Reserved
9	SCIRXINTA (SCIA_RX)	SCITXINTA (SCIA_TX)	SCIRXINTB (SCIB_RX) / LINA_INT0	SCITXINTB (SCIB_TX) / LINA_INT1	ECAN0INTA (CANA_1)	ECAN1INTA (CANA_2)	ECAN0INTB (CANB_1)	ECAN1INTB (CANB_2)
10	EPWM9_TZINT / ADCINT1	EPWM10_TZINT / ADCINT2	EPWM11_TZINT / ADCINT3	EPWM12_TZINT / ADCINT4	EPWM13_TZINT / ADCINT5	EPWM14_TZINT / ADCINT6	EPWM15_TZINT / ADCINT7	EPWM16_TZINT / ADCINT8
11	CLA1_INT1 / EPWM9_INT7 / MTOCIPCINT1	CLA1_INT2 / EPWM10_INT / MTOCIPCINT2	CLA1_INT3 / EPWM11_INT / MTOCIPCINT3	CLA1_INT4 / EPWM12_INT / MTOCIPCINT4 /	CLA1_INT5 / EPWM13_INT	CLA1_INT6 / EPWM14_INT	CLA1_INT7 / EPWM15_INT	CLA1_INT8 / EPWM16_INT
12	XINT3	XINT4 / C28FLSINGERR	XINT5	XINT6 / C28RAMSINGERR	XINT7 / C28RAMACCVIOL	Reserved	LVF	LUF

The PIE and CPU interrupt numbers for the c28x processors F2807x, F2837xS, F2837xD, F2838x, F28004x, F28002x, and F28003x that support 12×16 interrupts are:

PIE and CPU Interrupt Numbers for F2807x, F2837xS, F2837xD, F2838x, F28004x, F28002x, and F28003x Processors

PIE ⇒	1	2	3	4	5	6	7	8
CPU ⇓	1	2	3	4	5	6	7	8
1	ADCA1	ADCB1	ADCC1	XINT1	XINT2	ADCD1	TIMER 0	WAKE / WDOG
2	EPWM1_TZ	EPWM2_TZ	EPWM3_TZ	EPWM4_TZ	EPWM5_TZ	EPWM6_ TZ	EPWM7_TZ	EPWM8_TZ
3	EPWM1	EPWM2	EPWM3	EPWM4	EPWM5	EPWM6	EPWM7	EPWM8
4	ECAP1	ECAP2	ECAP3	ECAP4	ECAP5	ECAP6	ECAP7	Reserved
5	EQEP1	EQEP2	EQEP3	Reserved	CLB1	CLB2	CLB3	CLB4
6	SPIA_RX	SPIA_TX	SPIB_RX	SPIB_TX	MCBSPA_RX	MCBSPA_TX	MCBSPB_RX	MCBSPB_TX
7	DMA_CH1	DMA_CH2	DMA_CH3	DMA_CH4	DMA_CH5	DMA_CH6	Reserved	Reserved
8	I2CA	I2CA_FIFO	I2CB	I2CB_FIFO	SCIC_RX	SCIC_TX	SCID_RX	SCID_TX
9	SCIA_RX	SCIA_TX	SCIB_RX	SCIB_TX	CANA_0	CANA_1	CANB_0	CANB_1
10	ADCA_EVT	ADCA2	ADCA3	ADCA4	ADCB_EVT	ADCB2	ADCB3	ADCB4
11	CLA1_1	CLA1_2	CLA1_3	CLA1_4	CLA1_5	CLA1_6	CLA1_7	CLA1_8
12	XINT3	XINT4	XINT5	MPOST	FMC.DONE	VCU	FPU_OVERFLOW	FPU_UNDERFLOW

PIE ⇒	9	10	11	12	13	14	15	16
CPU ⇓	9	10	11	12	13	14	15	16
1	I2CA	SYS_ERR	ECATSYNC0 (CPU1 only)	ECATINTn (CPU1 only)	IPC0/CIPC0	IPC1/CIPC1	IPC2/CIPC2	IPC3/CIPC3
2	EPWM9_TZ	EPWM10_ TZ	EPWM11_TZ	EPWM12_TZ	EPWM13_TZ	EPWM14_TZ	EPWM15_TZ	EPWM16_TZ
3	EPWM9	EPWM10	EPWM11	EPWM12	EPWM13	EPWM14	EPWM15	EPWM16
4	FSITXA_INT1	FSITXA_INT2	FSITXB_INT1	FSITXB_INT2	FSIRXA_INT1	FSIRXA_INT2	FSIRXB_INT1	FSIRXB_INT2
5	SD1 / SDFM1	SD2/SDFM1	ECATRSTINTn (CPU1 only)	ECATSYNC1 (CPU1 only)	SDFM1DR1	SDFM1DR2	SDFM1DR3	SDFM1DR4
6	SPIC_RX	SPIC_TX	SPID_RX	SPID_TX	SDFM2DR1	SDFM2DR2	SDFM2DR3	SDFM2DR4
7	FSIRXC_INT1	FSIRXC_INT2	FSIRXD_INT1	FSIRXD_INT2	FSIRXE_INT1	FSIRXE_INT2	FSIRXF_INT1	FSIRXF_INT2
8	LINA_0/FSIRXG_INT1	LINA_1/FSIRXG_INT2	FSIRXH_INT1	FSIRXH_INT2	PMBUSA/CLB5	CLB6	UPPA (CPU1 only)/CLB7	CLB8
9	MCANSS_INT0(CPU1 only)	MCANSS_INT1 (CPU1 only)	MCANSS_ECC_CORR_PUL_INT (CPU1 only)	MCANSS_WAKE_AND_TS_PLS_INT (CPU1 only)	PMBUSA	CM_STATUS (CPU1 only)	USBA (CPU1 only)	Reserved
10	ADCC_EVT	ADCC2	ADCC3	ADCC4	ADCD_EVT	ADCD2	ADCD3	ADCD4
11	CMTOCPUxIPCINTR0	CMTOCPUxIPCINTR1	CMTOCPUxIPCINTR2	CMTOCPUxIPCINTR3	CMTOCPUxIPCINTR4	CMTOCPUxIPCINTR5	CMTOCPUxIPCINTR6	CMTOCPUxIPCINTR7
12	EMIF_ ERROR	RAM_CORRECTABLE_ERROR/ECAP6INT2	FLASH_CORRECTABLE_ERROR/ECAP7INT2	RAM_ACCESS_VIOLATION	SYS_PLL_ SLIP/CPUxCRC_INT	AUX_PLL_SLIP//CLA1CRC_INT	CLA OVER FLOW	CLA UNDERFLOW

The PIE and CPU interrupt numbers for the c281x processors are:

PIE and CPU Interrupt Numbers for C281x Processors

PIE ⇒	1	2	3	4	5	6	7	8
CPU ⇓	1	2	3	4	5	6	7	8
1	PDPINTA (EV-A)	PDPINTB (EV-B)	Reserved	XINT1	XINT2	ADCINT (ADC)	TINT0 (TIMER 0)	WAKEINT (LPM/WD)
2	CMP1INT (EV-A)	CMP2INT (EV-A)	CMP3INT (EV-A)	T1PINT (EV-A)	T1CINT (EV-A)	T1UFINT (EV-A)	T1OFINT (EV-A)	Reserved
3	T2PINT (EV-A)	T2CINT (EV-A)	T2UFINT (EV-A)	T2OFINT (EV-A)	CAPINT1 (EV-A)	CAPINT2 (EV-A)	CAPINT3 (EV-A)	Reserved
4	CMP4INT (EV-B)	CMP5INT (EV-B)	CMP6INT (EV-B)	T3PINT (EV-B)	T3CINT (EV-B)	T3UFINT (EV-B)	T3OFINT (EV-B)	Reserved
5	T4PINT (EV-B)	T4CINT (EV-B)	T4UFINT (EV-B)	T4OFINT (EV-B)	CAPINT4 (EV-B)	CAPINT5 (EV-B)	CAPINT6 (EV-B)	Reserved
6	SPIRXINTA (SPI)	SPITXINTA (SPI)	Reserved	Reserved	MRINT (McBSP)	MXINT (McBSP)	Reserved	Reserved
7	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved
8	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved
9	SCIRXINTA (SCI-A)	SCITXINTA (SCI-A)	SCIRXINTB (SCI-B)	SCITXINTB (SCI-B)	ECAN0INT (CAN)	ECAN1INT (CAN)	Reserved	Reserved
10	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved
11	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved
12	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved	Reserved

Version History

Introduced in R2016b

C28x Hardware Interrupt

Description

Vectorized Output

Examples

Synchronizing ePWM and eCAP Modules using Time-Base Counter Synchronization

ADC-PWM Synchronization Using ADC Interrupt

Asynchronous Scheduling

Field-Oriented Control of PMSM with Quadrature Encoder Using C2000 Processors

Schedule a Multi-Rate Controller for a Permanent Magnet Synchronous Machine

Photovoltaic Inverter with MPPT Using Solar Explorer Kit

Ports

Input

SimIRQ — Simulation interrupt input port scalar

Dependencies

Output

IRQ — Generate interrupt request Scalar

Parameters

CPU interrupt number — Specify vector of CPU interrupt [1 1] (default) | integer in [1, 8]

PIE interrupt number — Specify a vector of PIE interrupt [1 2] (default)

Simulink task priorities — Provides relative importance of tasks associated with the asynchronous interrupts [30 26] (default)

Preemption flags: preemptable-1, non-preemptable-0 — Specify a vector of preemption flags for the interrupts 0 0 (default)

Enable simulation input — Enable simulation ports to block off (default) | on

PIE and CPU interrupt numbers

Version History

SimIRQ — Simulation interrupt input port
scalar

IRQ — Generate interrupt request
`Scalar`

CPU interrupt number — Specify vector of CPU interrupt
`[1 1]` (default) | integer in [1, 8]

PIE interrupt number — Specify a vector of PIE interrupt
`[1 2]` (default)

Simulink task priorities — Provides relative importance of tasks associated with the asynchronous interrupts
`[30 26]` (default)

Preemption flags: preemptable-1, non-preemptable-0 — Specify a vector of preemption flags for the interrupts
`0 0` (default)

Enable simulation input — Enable simulation ports to block
`off` (default) | `on`