Frequency Estimator

Estimate carrier frequency offset (CFO) using open-loop approach

Since R2026a

Libraries:
Wireless HDL Toolbox / Modulation

Description

The Frequency Estimator block estimates the carrier frequency offset (CFO) of an input sequence by using the open-loop approach. This approach uses either a correlation-based algorithm or an FFT-based algorithm for estimation. The block accepts data and a control signal to indicate valid data and outputs frequency offset estimates and a control signal to indicate a valid data output. The block supports both data aided and non-data aided modulation removal methods.

The block supports scalar inputs and provides a hardware-friendly interface and architecture to generate HDL code with HDL Coder™. You can use this block in custom communications systems, such as quadrature phase shift keying (QPSK), and in satellite communications, such as Digital Video Broadcasting - Satellite - Second Generation (DVB-S2) and Consultative Committee for Space Data Systems (CCSDS) receivers, to determine and correct frequency offsets for reliable carrier synchronization.

Examples

New

Frequency Offset Estimation for QPSK Modulated Signals

Estimate CFO for QPSK-modulated signals.

Since R2026a
Open Script

New

QPSK Transmitter and Receiver

Design and verify a QPSK transmitter and receiver for hardware.

Since R2026a
Open Script

Ports

Input

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data — Input data
complex scalar

Input data, specified as a complex-valued scalar.

For correlation-based implementation, the input length must be equal to the averaging length. For FFT-based implementation, the input length must be equal to the FFT length.

The block supports double and single data types for simulation but not for HDL code generation. For HDL code generation, the block supports signed fixed point data type and the word length must be in the range 8 to 32 and the fraction length must be less than or equal to word length – 2.

Data Types: single | double | int8 | int16 | int32 | fixed point
Complex Number Support: Yes

valid — Signal to indicate valid input data
scalar

Signal to indicate valid input data, specified as a Boolean scalar.

The control signal at this port indicates when samples from the data and refData input ports are valid. When the value at this port is 1, the block captures the values on the data and refData input ports. When the value at the port is 0, the block ignores the values on the data and refData input ports.

Data Types: Boolean

refData — Reference data
real scalar | complex scalar

Reference data, specified as a real or a complex-valued scalar.

Dependencies

To enable this port, set the Modulation removal parameter to Data aided.

Data Types: single | double | int8 | int16 | int32 | fixed point
Complex Number Support: Yes

reset — Signal to clear internal states
scalar

Signal to clear internal states, specified as a Boolean scalar. When this value is 1, the block stops the current calculation and clears all internal states.

Dependencies

To enable this port, select the Enable reset input port parameter.

Data Types: Boolean

Output

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freqEst — Estimated frequency offset
real scalar

Estimated frequency offset normalized by input sample rate, returned as a real-valued scalar.

Correlation-based Implementation

In correlation-based implementation, the output data type is same as the input data for double and single data types. For the fixed point data type, the output data type is fixdt(1,WL,WL), where WL is the word length.

For the non-data aided method, WL is equal to nextpow2(N) + nextpow2(M) + (2 x RWL) + 3, where:
- M is the modulation order.
- N is the correlation length.
- RWL is the modulation removed symbol word length. For this block, RWL value is fixed at 8.
For the data aided method, WL is equal to nextpow2(N) + (2 x RWL) + 3.

FFT-based Implementation

In the FFT-based implementation, the output data type is the same as the input data for double and single data types. For the fixed point data type, the output data type is fixdt(1,WL,WL).

For the non-data aided method, WL is equal to nextpow2(FFTLength) + nextpow2(M), where:
- FFTLength is the FFT length.
- M is the modulation order.
For the data aided method, WL is equal to nextpow2(FFTLength).

Data Types: single | double | int16 | int32 | fixed point

valid — Signal to indicate valid output data
scalar

Signal to indicate valid output data, returned as a Boolean scalar.

The control signal at this port indicates when the data at the freqEst output port is valid. When estimated samples are available at the freqEst output port, the block sets the value at this port to 1.

Data Types: Boolean

Parameters

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Estimation algorithm — Estimation algorithm
`Correlation-based` (default) | `FFT-based`

Select the estimation algorithm to estimate the frequency offset from one of these options:

Correlation-based — Use the differential detection and averaging for estimation.
FFT-based — Use the fast Fourier transform (FFT) for frequency estimation.

For more information, see Algorithms.

Correlation length — Correlation length
`4` (default) | positive integer in the range 1 to 63

Specify the correlation length as a positive integer in the range 1 to 63.

Dependencies

To enable this parameter, set the Estimation algorithm parameter to Correlation-based.

FFT length — FFT length
1024 (default) | power of 2 in the range 4 to 65,536

Specify the FFT length as of power of 2 in the range 4 to 65,536.

Dependencies

To enable this parameter, set the Estimation algorithm parameter to FFT-based.

Averaging length — Averaging length
`1024` (default) | positive integer less than or equal to 65,536 and greater than correlation length

Specify the averaging length as a positive integer less than or equal to 65,536 and greater than the correlation length. The averaging length must be less than or equal to the length of the continuous sequence of known reference symbols when you select the Data aided method.

Dependencies

To enable this parameter, set the Estimation algorithm parameter to Correlation-based.

Modulation removal — Modulation removal
`Non-data aided` (default) | `Data aided`

Select one of these modulation removal methods:

Non-data aided — Use this method when you know only the modulation type of the input data. Select the desired modulation type using the Modulation parameter.
Data aided — Use this method when you already know the modulated symbols of the input data. Provide the known modulated symbols through the refData input port.

Modulation — Modulation type
`QPSK` (default) | `BPSK` | `8-PSK`

Select the modulation type as one of the following:

BPSK — Binary phase shift keying
QPSK — Quadrature phase shift keying
8-PSK — 8-phase shift keying

Dependencies

To enable this parameter, set the Modulation removal parameter to Non-data aided.

Enable reset input port — Option to reset signal
`off` (default) | `on`

Select this parameter to enable the reset input port.

Algorithms

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The Frequency Estimator block is designed to estimate the CFO of an observed signal. The block supports FFT-based and correlation-based algorithms to support different requirements.

The observed signal, c_n, is represented as

$c_{n} = x_{n} e^{j (w n + θ)}, 0 \leq n \leq P - 1.$

For the data aided method x_n is the known reference symbols such that the magnitude of x_n is constant, and for the non-data aided method, x_n is the modulated symbols.

$w = 2 π (\frac{f_{0}}{f_{s}}) ,$
where f₀ is the carrier frequency offset and f_s is the sampling frequency of the observed sequence.
θ is an unknown constant phase offset.
P is considered the averaging length for the correlation-based algorithm and as FFT length for the FFT-based algorithm.

The modulation removed symbol

$r_{n} = e^{j ϕ} .$

For the data aided method,

$ϕ = a r g (c_{n}) - a r g (x_{n})$

and for the non-data aided method,

$ϕ = a r g (c_{n}) < < n e x t p o w 2 (M) .$

Where, ø is quantized with the phase quantization word length fixed at 8 and wrapped to lie within the range -π to π.

Correlation-Based Estimation

This section describes the correlation-based estimation algorithm used to estimate the frequency offset. The estimated frequency offset is calculated as:

$\frac{{\hat{f}}_{0}}{f_{s}} = [\frac{1}{π (N + 1) M}] * \arg | \sum_{m = 1}^{N - 1} R_{m} |,$

where:

For data aided cases

$R_{m} = \frac{1}{L - m} \sum_{n = m}^{L - 1} r_{n} * c o n j (r_{n - m}^{})$
For non-data aided cases

$R_{m} = \frac{1}{L} \sum_{n = 0}^{L - 1} r_{n} * c o n j (r_{n - m}^{})$

The estimation range is

$\frac{- 1}{(N + 1) M} \leq \frac{{\hat{f}}_{0}}{f_{s}} \leq \frac{1}{(N + 1) M},$

where M is the modulation order, N is the correlation length, and L is the averaging length. For data aided cases, M is equal to 1.

FFT-Based Estimation

This section describes the FFT-based estimation of frequency offsets. In FFT-based estimation, the spectrum of the sequence r_n is divided into frequency bins. The edges of these bins represent the potential estimates of the algorithm. The actual estimate is the edge nearest to the frequency offset in the observed sequence.

The estimation range is

$\frac{- 1}{2 M} \leq \frac{{\hat{f}}_{0}}{f_{s}} \leq \frac{1}{2 M},$

where M is the modulation order. For data aided cases, M is equal to 1.

Latency

The latency of the block varies with the estimation algorithm and modulation removal. For the Correlation-based implementation, the latency also depends on the input word length.

This figure shows a sample output of the block with input word length 16 and with default configuration. The latency of the block is 1089 clock cycles.

Frequency Estimator Block Latency for Correlation-based

This figure shows a sample output of the block when you set the Estimation algorithm parameter to FFT-based, FFT length to 1024, Modulation removal parameter to Data aided, and the Modulation parameter to QPSK. The latency of the block is 2170 clock cycles.

Frequency Estimator Block Latency for FFT-based

Performance

This table shows the resource and performance data synthesis results of the block for the default configuration when you set the Estimation algorithm parameter to Correlation-based, Correlation length parameter to 4, Averaging length parameter to 1024, Modulation removal parameter to Non-data aided, and Modulation parameter to QPSK. The input data provided is of type fixdt(1,16,14). The generated HDL targets to the AMD^® Zynq^® UltraScale+™ MPSoC - ZCU102 Evaluation Board. The design achieves a clock frequency of 474.16 MHz.

CLB LUTs	CLB Registers	DSPs	Block RAMs
3355	4029	9	0

References

[1] Mengali, Umberto, and Aldo N. D’Andrea. Synchronization Techniques for Digital Receivers. Springer US, 1997. https://doi.org/10.1007/978-1-4899-1807-9.

[2] Luise, M., and R. Reggiannini. “Carrier Frequency Recovery in All-Digital Modems for Burst-Mode Transmissions.” IEEE^® Transactions on Communications 43, no. 2/3/4 (Feb. 1995): 1169–78.

Extended Capabilities

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C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^® accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).
SynthesisAttributes	Specifies the synthesis attributes for the blocks and block output signals in the model. The generated HDL code contains these attributes. For more information, see SynthesisAttributes (HDL Coder).

Restrictions

You cannot generate HDL for this block inside a Resettable Synchronous Subsystem (HDL Coder).

Version History

Introduced in R2026a

Frequency Estimator

Description

Examples

Frequency Offset Estimation for QPSK Modulated Signals

QPSK Transmitter and Receiver

Ports

Input

data — Input data
complex scalar

valid — Signal to indicate valid input data
scalar

refData — Reference data
real scalar | complex scalar

Dependencies

reset — Signal to clear internal states
scalar

Dependencies

Output

freqEst — Estimated frequency offset
real scalar

valid — Signal to indicate valid output data
scalar

Parameters

Estimation algorithm — Estimation algorithm
`Correlation-based` (default) | `FFT-based`

Correlation length — Correlation length
`4` (default) | positive integer in the range 1 to 63

Dependencies

FFT length — FFT length
1024 (default) | power of 2 in the range 4 to 65,536

Dependencies

Averaging length — Averaging length
`1024` (default) | positive integer less than or equal to 65,536 and greater than correlation length

Dependencies

Modulation removal — Modulation removal
`Non-data aided` (default) | `Data aided`

Modulation — Modulation type
`QPSK` (default) | `BPSK` | `8-PSK`

Dependencies

Enable reset input port — Option to reset signal
`off` (default) | `on`

Algorithms

Correlation-Based Estimation

FFT-Based Estimation

Latency

Performance

References

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Version History

See Also

Objects

Frequency Estimator

Description

Examples

Frequency Offset Estimation for QPSK Modulated Signals

QPSK Transmitter and Receiver

Ports

Input

data — Input data complex scalar

valid — Signal to indicate valid input data scalar

refData — Reference data real scalar | complex scalar

Dependencies

reset — Signal to clear internal states scalar

Dependencies

Output

freqEst — Estimated frequency offset real scalar

valid — Signal to indicate valid output data scalar

Parameters

Estimation algorithm — Estimation algorithm Correlation-based (default) | FFT-based

Correlation length — Correlation length 4 (default) | positive integer in the range 1 to 63

Dependencies

FFT length — FFT length 1024 (default) | power of 2 in the range 4 to 65,536

Dependencies

Averaging length — Averaging length 1024 (default) | positive integer less than or equal to 65,536 and greater than correlation length

Dependencies

Modulation removal — Modulation removal Non-data aided (default) | Data aided

Modulation — Modulation type QPSK (default) | BPSK | 8-PSK

Dependencies

Enable reset input port — Option to reset signal off (default) | on

Algorithms

Correlation-Based Estimation

FFT-Based Estimation

Latency

Performance

References

Extended Capabilities

C/C++ Code Generation Generate C and C++ code using Simulink® Coder™.

HDL Code Generation Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

Version History

See Also

Objects

data — Input data
complex scalar

valid — Signal to indicate valid input data
scalar

refData — Reference data
real scalar | complex scalar

reset — Signal to clear internal states
scalar

freqEst — Estimated frequency offset
real scalar

valid — Signal to indicate valid output data
scalar

Estimation algorithm — Estimation algorithm
`Correlation-based` (default) | `FFT-based`

Correlation length — Correlation length
`4` (default) | positive integer in the range 1 to 63

FFT length — FFT length
1024 (default) | power of 2 in the range 4 to 65,536

Averaging length — Averaging length
`1024` (default) | positive integer less than or equal to 65,536 and greater than correlation length

Modulation removal — Modulation removal
`Non-data aided` (default) | `Data aided`

Modulation — Modulation type
`QPSK` (default) | `BPSK` | `8-PSK`

Enable reset input port — Option to reset signal
`off` (default) | `on`

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.