LTE Gold Sequence Generator

Generate Gold sequence

Libraries:
Wireless HDL Toolbox / Utilities

Description

The LTE Gold Sequence Generator block returns Gold sequences generated using the polynomial and shift length specified by LTE standard TS 36.212 [1]. Gold codes are pseudorandom sequences that have high autocorrelation and low crosscorrelation. Due to these properties, Gold codes are widely used in communications systems. For example, they are used to separate different mobile cells operating on the same frequency. LTE systems use a Gold sequence generator for reference symbols and for scrambling/descrambling data, such as in MIB and SIB coding and decoding.

This block provides minimal latency by implementing the shift register initialization in parallel.

Use the load control signal to indicate when the init value is valid. Use the enable control signal to request the next Gold sequence value. The valid signal indicates when an output sample is available. The first output sample is ready three cycles after enable is asserted. The data and valid outputs follow the pattern of the enable input.

Examples

Descrambling with Gold Sequence Generator

Use LTE Gold Sequence Generator block to implement LTE descrambler.

Open Model

Parallel Gold Sequence Generation

Use LTE Gold Sequence Generator block to generate multiple sequences in parallel for use in channel estimation.

Open Model

Ports

Input

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load — Load initial shift register value
scalar

When this control signal is set to true (1), the block loads the value on the init port into the shift register. You can use this signal to restart the sequence at any point in time.

Data Types: Boolean

init — Initial shift register value
scalar | vector

Initial shift register value, specified as a ufix31 number representing the 31 binary values. To generate multiple Gold sequence outputs in parallel, specify a vector of initial values to represent multiple channels.

Data Types: ufix31

enable — Enable sequence generation
scalar

When this control signal is set to true (1), it enables Gold sequence generation.

Data Types: Boolean

Output

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data — Generated Gold sequence
scalar | vector

Generated Gold sequence, returned as a Boolean scalar or vector, depending on the size of the init input. If init is a vector, then data is a vector of the same size, representing sequences on independent channels.

Data Types: Boolean

valid — Indicates valid output data
scalar

Control signal that indicates when the data output port is valid.

Data Types: Boolean

Algorithms

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To avoid long shift latency, the block applies the initial value as a parallel mask. To calculate the mask, the block divides the initial polynomial by the linear-feedback shift register polynomial.

Architecture diagram of the Gold sequence polynomial.

Performance

These resource and performance data are the synthesis results from the generated HDL targeted to an AMD^® Zynq^®-7000 ZC706 board. The design achieves a clock frequency of 625 MHz.

Resource	Uses
LUT	86
LUTRAM	0
FFS	107
Block RAM (16K)	0

References

[1] 3GPP TS 36.212. "Multiplexing and channel coding." 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Evolved Universal Terrestrial Radio Access (E-UTRA). URL: https://www.3gpp.org.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^® accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Version History

Introduced in R2018a

LTE Gold Sequence Generator

Description

Examples