LTE Symbol Modulator

Modulate data bits to complex LTE data symbols

Libraries:
Wireless HDL Toolbox / Modulation

Description

The LTE Symbol Modulator block maps a group of data bits to complex data symbols by using the modulation types supported by LTE standard TS 36.211 [1]. The block provides an architecture suitable for HDL code generation and hardware deployment. You can use this block in the development of an LTE transmitter.

The block accepts 1-bit of data at a time, along with control signals, and outputs a modulated complex symbol with a valid signal. Each complex symbol comprises a standard number of bits based on the modulation type, as shown in this table. If you provide a nonmultiple of modulation-order bits as an input, the block ignores the output symbol with insufficient or excessive bits. The modulation order is the number of bits per symbol.

Modulation Type	Modulation Order - Number of Bits Per Symbol
BPSK	1
QPSK	2
16-QAM	4
64-QAM	6
256-QAM	8

Examples

LTE Symbol Modulation of Data Bits

Use LTE Symbol Modulator block to modulate data bits to complex data symbols.

Open Script

Ports

Input

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data — Input data bits
scalar

Input data bits, specified as a scalar. The block accepts Boolean or ufix1 data bits.

Data Types: Boolean | fixdt(0,1,0)

valid — Indicate valid input data
scalar

Control signal that indicates if the input data is valid. When this value is 1 (true), the block accepts the values on the data input port. When this value is 0 (false), the block ignores the values on the data input port.

Data Types: Boolean

modSel — Modulation selection
integer

Select the modulation type by specifying its corresponding value shown in this table.

The modSel values are from 0 to 4. Each value represents a specific modulation type.

Value	Modulation Type
`0`	BPSK
`1`	QPSK
`2`	16-QAM
`3`	64-QAM
`4`	256-QAM

If you specify a value other than one listed in this table, the block displays a warning message and:

Applies QPSK modulation when load is 1 (true).
Continues with the current modulation when load is 0 (false).

For HDL code generation, specify this value in fixdt(0,3,0) format.

Dependencies

To enable this port, set the Modulation source parameter to Input port.

Data Types: fixdt(0,3,0) | double | single

load — Modulation control
scalar

Control signal to sample modulation.

When this value is 1 (true), the block applies the modulation based on the modSel value. When this value is 0 (false), the block ignores any changes in the modSel value and continues with the current modulation until load changes to 1 (true).

If the load value changes to 1 (true) during the block operation, the block resynchronizes and restarts modulation using the current value of modSel. This restart occurs whether or not the modSel value has changed. For example, if the block is operating in 256-QAM mode and the load value changes to 1 (true) after four of the eight required input bits are sent into the block, the block discards those first four bits and restarts its operation from the fifth bit.

If you do not apply the load value as 1 (true) at the start of block operation, by default, the block operates with QPSK modulation.

Dependencies

To enable this port, set the Modulation source parameter to Input port.

Data Types: Boolean

Output

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data — Modulated complex data symbols
scalar

Modulated complex data symbols, returned as a scalar.

Data Types: single | double | fixdt(1,wordlength,wordlength-2)
Complex Number Support: Yes

valid — Valid output data indication
scalar

Control signal that indicates if data from the data output port is valid. When this value is 1 (true), the block returns valid data on the data output port. When this value is 0 (false), the block ignores values on the data output port.

Data Types: Boolean

Parameters

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Main

Modulation source — Source for modulation type
`Property` (default) | `Input port`

To specify the modulation type by using the Modulation parameter, select Property. To specify the modulation type from the modSel port during run time, select Input port.

Modulation — Modulation type
`BPSK` (default) | `QPSK` | `16-QAM` | `64-QAM` | `256-QAM`

Select the modulation type.

Dependencies

To enable this parameter, set the Modulation source parameter to Property.

Data Types

Output data type — Output data type selection
`Custom` (default) | `double` | `single`

Specify the data type for the output data.

double and single data types are supported for simulation.

For simulation and HDL code generation, set this value to Custom.

Word length — Output word length
`16` (default) | integer in the range [3, 32]

Specify the output word length. This value must be an integer in the range [3, 32].

Dependencies

To enable this parameter, set the Output data type parameter to Custom.

Algorithms

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Output Waveforms

These figures show sample outputs of the block when operated with a fixed modulation type applied using the Modulation parameter and when operated with varied modulation types applied using the modSel input port. The latency of the block is equal to the sum of three clock cycles and the number of bits per symbol.

The block captures the output symbols at valid cycles.

This figure shows a Logic Analyzer waveform of the sample output when you select BPSK modulation by using the Modulation parameter. In this sample output, the latency of the block is 4.

This figure shows a Logic Analyzer waveform of the sample output when you select BPSK, QPSK, 16-QAM, 64-QAM, and 256-QAM modulations by using the modSel input port. The latency of the block varies with the modulation selection.

Performance

This table shows the resource and performance data synthesis results of the block when using the modSel input port as the modulation source and an output word length of 16. The generated HDL is targeted to an AMD^® Zynq^®- 7000 ZC706 evaluation board. The design achieves a clock frequency of 872 MHz.

Resource	Number Used
Slice LUTs	61
Slice Registers	67
DSP48	0

References

[1] 3GPP TS 36.211. "Physical channels and modulation." 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Evolved Universal Terrestrial Radio Access (E-UTRA). URL: https://www.3gpp.org.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^® accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

This block does not have any HDL Block Properties.

Version History

Introduced in R2019a

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R2023b: Change in output data type default settings

The default value for Output data type parameter is now changed to Custom. To see this change, double-click the block and then click Data Types tab.

LTE Symbol Modulator

Description