LTE Turbo Encoder

Encode binary samples using turbo algorithm

Libraries:
Wireless HDL Toolbox / Error Detection and Correction

Description

The LTE Turbo Encoder block implements the turbo encoder described by LTE standard TS 36.212 [1] using an interface and architecture optimized for HDL code generation and hardware deployment. The encoder is a parallel concatenated convolutional code (PCCC) with two 8-state constituent encoders and an internal interleaver. The first encoder operates on the input data stream, and the second encoder operates on an interleaved version of the input data. The block terminates each encoder output with independent tail bits. The coding rate is 1/3. The encoded output bits for each input bit are returned as a 3-by-1 vector, [S P1 P2]. In this vector, S is the systematic bit, and P1 and P2 are the parity bits from the two encoders.

This block uses a streaming sample interface with a bus for related control signals. This interface enables the block to operate independently of frame size, and to connect easily with other Wireless HDL Toolbox™ blocks. The block accepts and returns a value representing a single sample, and a bus containing three control signals. These signals indicate the validity of each sample and the boundaries of the frame. To convert a matrix into a sample stream and these control signals, use the Frame To Samples block or the whdlFramesToSamples function. For a full description of the interface, see Streaming Sample Interface.

The block can accept new input data after the previous frame is complete. Apply input frames with at least BlockSize + 16 idle cycles between them. The 16 cycles consists of 12 cycles for pipeline delays in the algorithm, and 4 cycles of tail bits. This latency does not vary with block size. Or, you can use the output signal ctrl.end to determine when the block is ready for new input.

This waveform shows an input frame of 40 samples, with 57 idle cycles between frames. The input and output ctrl buses are expanded to show the control signals. start and end show the frame boundaries, and valid qualifies the data samples. The optional tail1 and tail2 signals indicate the cycles when the tail bits from each encoder are valid.

Logic Analyzer waveform of LTE Turbo Encoder block input and output signals

Examples

Turbo Encode Streaming Samples

Use LTE Turbo Encoder block to encode data, and how to compare hardware-friendly design with results from LTE Toolbox™.

Open Script

Ports

Input

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data — Input sample
scalar

Input sample, specified as a binary scalar. double and single are supported for simulation but not for HDL code generation.

Data Types: single | double | Boolean | ufix1

ctrl — Control signals accompanying sample stream
`samplecontrol` bus

Control signals accompanying the sample stream, specified as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

start — Indicates the start of the input frame
end — Indicates the end of the input frame
valid — Indicates that the data on the input data port is valid

For more details, see Sample Control Bus.

Data Types: bus

blockSize — Turbo code block size
integer

Turbo code block size, specified as an integer. This value must be one of the 188 values specified in the LTE standard, from 40 to 6144 in these intervals: [40:8:512 528:16:1024 1056:32:2048 2112:64:6144].

Dependencies

This port appears when you set Block size source to Input port.

Data Types: single | double | uint16 | fixdt(0,13,0)

Output

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data — Encoded sample stream
3-by-1 column vector

Encoded sample stream, returned as a 3-by-1 column vector. Each encoded sample is represented by one systematic bit and two parity bits.

The output data type matches the input data type.

Data Types: single | double | Boolean | ufix1

ctrl — Control signals accompanying sample stream
`samplecontrol` bus

Control signals accompanying the sample stream, returned as a samplecontrol bus. The bus includes the start, end, and valid control signals, which indicate the boundaries of the frame and the validity of the samples.

start — Indicates the start of the output frame
end — Indicates the end of the output frame
valid — Indicates that the data on the output data port is valid

For more details, see Sample Control Bus.

Data Types: bus

tail1, tail2 — Indicate trellis termination cycles
scalar

Use the optional tail1 and tail2 output ports to indicate the location of the tail bits in the output data stream. These signals are 1 (true) for the cycles that correspond to the tail bits for each encoder.

The block returns the tail bits in the order specified by the LTE standard TS 36.212 [1]. Each encoder returns two cycles of encoded tail bits.

Cycle	1	2	3	4
tail1	1	1	0	0
tail2	0	0	1	1
data	[E1in_K E1out_K E1in_K+1]	[E1out_K+1 E1in_K+2 E1out_K+2]	[E2in_K E2out_K E2in_K+1]	[E2out_K+1 E2in_K+2 E2out_K+2]

Dependencies

Enable these ports by selecting Enable trellis termination valid ports.

Data Types: Boolean

Parameters

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Block size source — How to specify the block size
`Input port` (default) | `Property`

Select whether you specify the block size with an input port or enter a fixed value as a parameter. If you select Property, the Block size parameter appears. If you select Input port, the blockSize port appears.

Block size — Turbo code block size
`6144` (default)

Turbo code block size, specified as an integer. This value must be one of the 188 values specified in the LTE standard, from 40 through 6144 in these intervals: [40:8:512 528:16:1024 1056:32:2048 2112:64:6144]. This value is registered for each frame, when ctrl.start = 1 (true).

Dependencies

This parameter appears when you set Block size source to Property.

Enable trellis termination valid ports — Enable ports that indicate the tail bit output samples
off (default) | on

When you select this parameter, the tail1 and tail2 ports appear on the block. These ports return control signals that indicate the cycles when the output samples are the tail bits for each encoder.

Tips

You cannot use this block inside an Enabled Subsystem or Resettable Subsystem.

Algorithms

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For a hardware implementation, storing the interleave indices is not practical. Supporting the 188 LTE block sizes would require 4 Mb of memory. Therefore, the algorithm uses the interleave specification to compute the indexes from the block size. This equation defines the interleave pattern:

$\prod (i) = (f_{1} \cdot i + f_{2} \cdot i^{2}) \mod K$

K is the block size, i = 0, 1, …, (K – 1), and f₁ and f₂ are defined in the LTE standard TS 36.212 [1].

Calculation of the indexes is simplified based on these equations:

$\begin{array}{l} π (i + 1) = {\begin{cases} π (i) + g (i) if π (i) + g (i) < K \\ π (i) + g (i) - K otherwise \end{cases} \\ π (0) = 0 \end{array}$

$\begin{array}{l} g (i + 1) = {\begin{cases} g (i) + 2 f_{2} if g (i) + 2 f_{2} < K \\ g (i) + 2 f_{2} - K otherwise \end{cases} \\ g (0) = f_{1} + f_{2} \end{array}$

Therefore, the block stores f₁ and f₂ in memory, and uses those two constants and four adders to calculate the interleave indexes.

Architecture diagram of the turbo encode algorithm

When Block size source is set to Property, the block uses two constant coefficients to derive the read addresses for the fixed block size. When Block size source is set to Input port, the algorithm saves the 188 pairs of coefficients in a ROM (< 5 Kb). Then the block reads the matching pair at run time to derive the interleave memory read addresses.

Performance

These resource and performance data are the synthesis results from the generated HDL targeted to an AMD^® Zynq^®-7000 ZC706 board. The implementation is for a fixed block size of 6144 samples. The design achieves 312.5 MHz clock frequency.

Resource	Uses
LUT	253
LUTRAM	2
FFS	222
BRAM	0.5

The RAM size grows with block size. When you enable the block size port, RAM sufficient for the largest block size is used.

References

[1] 3GPP TS 36.212. "Multiplexing and channel coding." 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; Evolved Universal Terrestrial Radio Access (E-UTRA). URL: https://www.3gpp.org.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink^® accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is `0`. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is `0`. For more details, see OutputPipeline (HDL Coder).

Version History

Introduced in R2017b

LTE Turbo Encoder

Description