DVB-S2 HDL Transmitter

Model Architecture

The BBFRAME Generator block generates BBFRAME from the user packets. The FECFRAME Generator block encodes the BBFRAME using BCH and LDPC coding, and interleaves the encoded frame to generate an FECFRAME. The Symbol Modulator block generates the xFECFRAME by mapping the FECFRAME bits to modulation symbols. The PLFRAME Generator block generates the PLHEADER, pilot symbols, and dummy frames, and multiplexes them with the xFECFRAME bits. The PL Data Scrambler block scrambles the multiplexer output to generate a PLFRAME. The RRC Filtering block pulse shapes the PLFRAME symbols to generate the transmitter waveform.

This figure shows the transmitter frame structure.

File Structure

This example uses supporting files.

System Interface

The figure shows the top-level overview of the dvbs2hdlTransmitter model.

Model Inputs

Model Outputs:

Model Structure

This figure shows the structure of the DVB-S2 HDL transmitter subsystem. The subsystem comprises BB Frame Generator, FEC Encoder, DVB-S2 HDL Interleaver, Symbol Modulator, PL Frame Generator, PL Data Scrambler, and RRC Transmit Filter subsystems.

BB Frame Generator

The BB Frame Generator subsystem comprises BB Header and Data CRC Generator, Data Store FIFO, Multiplexer, and BB Scrambler subsystems. The BB Header and Data CRC Generator subsystem generates BB header, discards the SYNC bits, appends CRC bits to each packet using the General CRC Generator HDL Optimized block, and appends padding bits to the data field for each frame. The Data Store FIFO subsystem stores the data field of each frame in a RAM buffer and reads it out after the BB header. The Multiplexer subsystem multiplexes the BB header and data field. The BB Scrambler subsystem scrambles the BB header and data field to generate a BBFRAME.

FEC Encoder

The FEC Encoder subsystem encodes the input bits with BCH Encoder subsystem followed by LDPC Encoder subsystem. For more information, see DVB-S2 HDL BCH Encoder and DVB-S2 HDL LDPC Encoder examples.

DVB-S2 HDL Interleaver

The DVB-S2 HDL Interleaver subsystem stores encoded bits from the LDPC Encoder subsystem inside the RAM subsystem. The RAM Address Generator subsystem generates read and write addresses for the RAM for interleaving.

In the RAM Address Generator subsystem, the nRows and nColumns subsystem stores the number of rows and columns of each possible configuration in lookup tables (LUT). Based on the MODCOD and FECFrame parameters, the subsystem determines the number of rows and columns for interleaving. The Read Offset Address subsystem generates the interleaver indices of each frame as an offset address. The subsystem reads only two bits are read for QPSK, three bits for 8-PSK, four bits for 16-APSK, and five bits for 32-APSK every eight time steps. This process ensures that each symbol covers eight time steps of the interleaver, which is equal to one symbol duration. The Generate and Add Read Base Address subsystem adds the offset address with a base read address to get the address of the bits that are stored in the RAM. The Parameter Store FIFO subsystem stores the parameters and reads them at the start of each frame.

This table shows the rows and columns for deinterleaving in each of the configurations.

    Modulation    Rows (Normal)    Rows (Short)    Columns
    __________    _____________    ____________    _______

     QPSK             64800           16200           1   
     8-PSK            21600           5400            3   
     16-APSK          16200           4050            4   
     32-APSK          12960           3240            5   

Symbol Modulator

The Symbol Modulator subsystem comprises DVB-S2 Symbol Modulator block that maps the input bits to the corresponding modulation symbols.

PL Frame Generator

The PL Frame Generator subsystem stores the modulated symbols in the RAM FIFO subsystem. The PL Header Generator subsystem generates the PLHEADER for each frame and stores it in the RAM FIFO subsystem. When symbols corresponding to a frame are ready in the RAM, the PL Frame Generator subsystem outputs the PLHEADER, pilot symbols, and data symbols according to the frame structure specified in [ 1 ]. When the symbols corresponding to a frame are not ready, the Dummy Frame Generator subsystem inside the RAM FIFO subsystem outputs dummy frames. The Multiplexer subsystem multiplexes the PLHEADER, pilot symbols, data symbols, and dummy frames to generate a unscrambled PLFRAME. The PL Data Scrambler subsystem scrambles the data field excluding the PLHEADER. The scrambling starts after the PLHEADER of each frame and continues until the end of the frame.

RRC Transmit Filter

The RRC Transmit Filter subsystem upsamples the input by a factor of four and uses the Discrete FIR Filter block with an RRC impulse response to pulse shape the PLFRAME symbols.

Run Model

Set the symbol rate, MODCOD, FECFrame type, input stream format, and user packet length on the mask of the Input Configuration subsystem and run the dvbs2hdlTransmitter model. Set the same symbol rate for the Input Configuration subsystem in the dvbs2hdlTransmitter model, the DVB-S2 Tx subsystem of the dvbs2hdlTransmitterCore model reference. Alternatively, execute this command at the MATLAB Command Window to run the model.

sim dvbs2hdlTransmitter

The MODCOD and FECFrame must be row vectors. Each element of the row vectors corresponds to the values of MODCOD and FECFrame in a frame.

Verification and Results

Run the model to display the transmitter spectrum, error plot between the reference waveform and simulation output, and relative mean squared error of the simulation output.

### Searching for referenced models in model 'dvbs2hdlTransmitter'.
### Found 1 model reference targets to update.
### Starting serial model reference simulation build.
### Successfully updated the model reference simulation target for: dvbs2hdlTransmitterCore

Build Summary

Model reference simulation targets:

Model                    Build Reason                                                Status                        Build Duration
=================================================================================================================================
dvbs2hdlTransmitterCore  Target (dvbs2hdlTransmitterCore_msf.mexw64) did not exist.  Code generated and compiled.  0h 5m 45.465s 

1 of 1 models built (0 models already up to date)
Build duration: 0h 5m 59.717s


Simulation Completed. Running verification script...
Relative mean squared error (dB) between the simulink output and reference = Real: -79.6448 Imag: -79.6563

HDL Code Generation

To generate the HDL code for this example, you must have HDL Coder™. Use makehdl and makehdltb functions to generate HDL code and HDL test bench for the DVB-S2 HDL transmitter subsystem. The test bench generation time depends on the simulation time.

The resulting HDL code is synthesized for a Xilinx® Zynq® UltraScale+ RFSoC ZCU111 board. This table shows the post place and route resource utilization. The maximum frequency of operation is 365 MHz.

      Resources      Usage
    _____________    _____

    CLB LUT          10701
    CLB Registers    9024 
    RAMB36           99   
    RAMB18           6    
    DSP48            42   

References