Simulink to VHDL using VHDL Coder but "Data Type Conversion" blocks don't compile
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Hello,
I have a simulink model that compiles and runs perfectly fine in Simulink. The model has several Data Type Conversion blocks that convert some floating point values to fixed point values. Standard, taking in inputs and converting to fixed point to increase efficiency.
When I run the VHDL Coder I get the following error:
For the block 'untitled/Data Type Conversion' Illegal conversion to/from double and fixed-point--operation not possible in untitled/Data Type Conversion.
Any ideas what could be wrong?
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Tim McBrayer
2011-8-16
HDL Coder supports the Data Type Conversion block, but as the error message states it cannot convert between doubles and fixed-point values. MATLAB doubles are in general not synthesizable. Even if they were, the hardware necessary to convert from a double representation (possibly IEEE-754, but not actually defined for synthesis) would be significant.
The best approach is to not use double values inside the subsystem you are generating code for. If you need double values in your test bench, make sure to convert them to integral or fixed-point values before they enter your design.
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William Knox
2012-1-14
To generate HDL code for a subsystem right-click on it and choose "Generate HDL Code for Subsystem".
If you right click on the subsystem and choose "HDL Coder Properties" and then choose "Generate" in the properties dialog box. HDL Coder will try and convert the whole model.
If you have say a clock source which outputs a double by default and then try and convert it to a bool for input to the aforementioned subsystem you will get errors since doubles are not supported in HDL Coder generation.
If you want to use a model with doubles on a FPGA or ASIC you must convert them to fixed-point types outside the subsystem that will converted to HDL code. HDL code generated with double or single data types is not synthesis-able. Please refer to the HDL Coder documentation for details on other restrictions.
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