For HDL Code Generation there are now several custom latency choices now available for divide, reciprocal and sqrt fixed-point operations .
HDL Reciprocal speed limitation?
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I've been looking at reciprocal function for Kintex-7 device.
Despite of various configurations I've tried on the HDL reciprocal block (pipelines, iterations), I could not get any speed faster than 215MHz for a 16-bit reciprocal.
Is this a hard limitation or there are some switches I can turn on to get faster speed?
Please advise, working with CoreGen or SysGen are bit too far from my standpoint now.
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