Set design verifiers parameters programmatically
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We have to set design verifiers 'MaxProcessTime' parameter programmatically so by using 'set_param' getting error like,
" block diagram does not have a parameter named 'MaxProcessTime'".
We have also tried sldvoptions but parameters are not reflecting in model.
Please provide effective solution for the same.
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回答(2 个)
Pat Canny
2022-1-4
Hi Aditi,
You should not use set_param to define the MaxProcess Time. The model itself has no parameter for this.
sldvdemo_cruise_control
optsModel = sldvoptions(bdroot);
optsCopy = optsModel.deepCopy;
optsCopy.MaxProcessTime = 120;
[ status, files ] = sldvrun(bdroot, optsCopy);
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jarvis
2025-8-1
Hi Aditi
I have tried to configure DVMaxProcessTime through scripting
set_param(COV_MODEL_NAME, 'DVMaxProcessTime', 1200);
But I faced problem like block_diagram does not have a parameter named 'DVMaxProcessTime'
then I found design verifier option or design verifier app should open then
the properties for design verifier will come in configuration set
Then we can use
set_param(COV_MODEL_NAME, 'DVMaxProcessTime', 1200);
The above process -> opening design verifier option (how to perform this through programitically)
Design Verifier Pane --> in this doc there is no information regarding that
have u found out how to achieve that
Devendra Bhave
2022-2-9
Use parameter DVMaxProcessTime to set maximum analysis time. You must save the model before calling sltest.testmanager.createTestForComponent() API.
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jarvis
2025-10-8,12:26
编辑:jarvis
2025-10-8,12:30
Thanks @Devendra Bhave
Its working. I can able to change Max process time.
I need some more help
While running above script which I have shared before for complex model (its has lot of LUTs and few extern variables) I'm facing error at the command
newTestCaseObj = sltest.testmanager.addTestsForMissingCoverage(testOpts, cvdata);
Errror: Problem facing while adding test case for missing coverage
What might be the reason for this ?
My assumption is due to increasein max process time its try to add different test cases in order to achieve higher coverage, while doing that its faced error. If Yes means How to solve this problem. Or How efficiently utilize design verifier
Devendra Bhave
2025-10-8,13:27
It is hard to answer definitively about this issue based on the above description.
Try Simulink Test Add Missing Coverage workflow with user interface (UI). This will open the Design Verifier UI, show analysis progress, and display any errors. A Design Verifier analysis timeout is usually not a serious error.
Contact MathWorks technical support for further assistance.
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