You can consider pipelining the design. See the timing related optimization section in HDL Coder https://www.mathworks.com/help/hdlcoder/speed-optimization.html
Some quick tips:
- Set some output pipelines, enable distributed pipelining.
- Consider using adaptive pipelining for inserting pipelines next to multipliers to enable better DSP mapping
- Use Critical Path Estimation report to see the location of the critical path in the model
- Identify critical path and right click on the block and input and output pipelines to break the critical path, delay balancing will kick in to add matching delays
