Multiply and add not correctly mapping to a single DSP slice

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Justin Kuric
Justin Kuric 2022-5-25
编辑： Jerome Davie 2024-6-21
I am using the design for DSP_subsys1 that is discussed in the mathworks example here.
The guidelines show that this design synthesizes to a single DSP48E1 slice with no additional logic, but the results I am getting are different.
The synthesized design only uses the multiplier on the DSP slice then includes additional LUTs and registers for the adders. The ports of the DSP slice that could be used for the adders are just tied to ground in the synthesized design despite being able to accomodate data types of these sizes. I am targeting a Virtex 7 device just like in the example and am using MATLAB 2021a with Vivado 2018.2 as the synthesis tool. Is there some setting in the HDL coder that I am missing?

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采纳的回答

Justin Kuric
Justin Kuric 2022-6-1
It turns out the issue had to do with how the resets were being set with the HDL coder. By default the HDL coder gives every delay block an asychronous reset. There is a global setting you can change so that it places synchronous resets instead. Once I did that I was able to map everything into a single DSP slice.
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Steven Hatcher
Steven Hatcher 2022-6-1
Hi Justin,
That's good to hear. I believe we give some warnings about the reset type depending on the target device that is set. We also have the HDL Code Advisor to detect this situation and give recommendations.
https://www.mathworks.com/help/hdlcoder/ug/check-for-global-reset-setting-for-xilinx-and-altera-devices.html
Steven

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更多回答（1 个）

Steven Hatcher
Steven Hatcher 2022-5-31
Hi Justin,
Are any of the adders using saturation or rounding logic that a Xilinx DSP48E1 would not natively support? Looking at the generated HDL code for the adders can help determine this.
Steven
  2 个评论
Justin Kuric
Justin Kuric 2022-6-1
I looked at the HDL code and it was not doing anything strange with the addition like it was trying to accomodate saturation.
Jerome Davie
Jerome Davie 2024-6-21
编辑：Jerome Davie 2024-6-21
There is additional info that's helpful for such a use case. I've been schooled on this issue and results are here: https://www.mathworks.com/matlabcentral/answers/2129931-hdl-coder-mult-add-uses-dsp48e1-fabric
Most important take away being that you should set the DSP style flag to 'ON' in the module's HDL block properties. I had found out about and applied the synchronous reset setting, but it still didn't work until that flag was set.
Regards,
Jerome

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