PMSM is programed in FPGA using HDL coder.
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Hi everyone,
I am intend to use HDL coder to build PMSM control application. I already saw Matlab's example ( Deploy Motor Control Algorithms to FPGA - Hardware Prototyping) for development this application. But, I have some confuse for this example 's architecturer. I have a question for that one:
- I don't see any periods for current loop and speed loop. In MCU platform, I usually use 10 kHz for control current loop and 1 kHz for speed loop. But in your example, I don't see anything to synch among subsystems ( speed loop, current loop, pwm, adc)
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Kiran Kintali
2022-6-15
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In the motor control demo project the current control algorithm and speed control runs on FPGA and processor respectively and they are modelled using model reference blocks (also known as model blocks).
The current control algorithm is configured to run at 25kHz (40e-6) and speed control algorithm is configured with 1kHz (1e-3), the sampling time for these referenced models is handled using sample time of inport from variable in data dictionary.
In the MODELING tab “ModelExplorer/External Data/focZynqData/Design Data/sampleTime” you can all the sample times configurations in the model
Additionally you can refer to
“'focZynqHdl/FOC_Velocity_Encoder/FOC_Current_Control/FOC_Current_Control/Phase_Current” inport sample time setting in “Execution’ tab.
ADC and PWM modules are available as IP cores in support packages/reference design of the demo, they are designed to be synchronized, and the interfaces to these modules are available in HDL Workflow advisor
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Kiran Kintali
2022-6-10
0 个投票
I think you are referring to this example. https://www.mathworks.com/videos/deploy-motor-control-algorithms-to-fpga-hardware-prototyping-1628756280693.html
Please note that Simulink handles the synchronization for you among the various modules in the model.
I would recommend Simulink onramp and https://www.mathworks.com/matlabcentral/fileexchange/58941-hdl-coder-evaluation-reference-guide for further guidance on this topic.
Please share sample models you have in mind and challenges if any w.r.to HDL code generation or deployment onto FPGA/HIL platform.
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