Atan2 block native floating point single HDL generation needs more pipelining

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Michael Pratt 2022-8-2

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https://ww2.mathworks.cn/matlabcentral/answers/1772925-atan2-block-native-floating-point-single-hdl-generation-needs-more-pipelining

编辑： Kiran Kintali 2024-5-29

Hi, I'm using the atan2 block with single precision to generate HDL and with the MAX latency of 42 clocks but it only achieves a clock rate of about 330 MHz (need more like 360 MHz) in my FPGA synthesis run. The critical path seems to be a stage of DSP48's chained together in cascade mode but without pipelining in the cascade. Is there a way to increase the pipelining internal to the atan2 block? Why does this block have no MIN or MAX range (MIN = MAX = 42). I think if you could just add more pipelining it would be able to run much faster. Retiming does not seems to be able to place registers where needed in this case.

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Bharath Venkataraman 2022-8-10

Do you need single precision support or do you think fixed-point would work as well? If fixed-point is an option, you can try the Complex to Magnitude Angle block.

Michael Pratt 2022-8-10

Yeah I did end up using the Complex to Magnitude Angle block. But I still think the atan2 block's timing could be improved significantly with a few underlying design changes. I discovered that if some bit slicing between the multiply and pipeline delays was moved to after the pipeline delays, synthesis was able to map the pipeline delays properly to the DSP48. The bit slicing gets in the way of optimal synthesis mapping in FPGAs (though the way it's implemented may be preferable for ASIC targets). I've often found that it's hard to make a design optimal for both ASIC and FPGA designs because often a design maps more efficiently for one than the other.

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Answer 1

Kiran Kintali 2024-5-29

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https://ww2.mathworks.cn/matlabcentral/answers/1772925-atan2-block-native-floating-point-single-hdl-generation-needs-more-pipelining#answer_1465096

编辑：Kiran Kintali 2024-5-29

Improved performance for Atan2 block in the R2024a release.

HDL Coder has enhanced the design implementation of the Atan2 block. The generated code for Atan2 blocks now has more pipelined stages and can be operated at higher frequency. This graph in the release note compares maximum frequency and maximum latency of an Atan2 block that has a single-precision floating-point input between R2024a and R2023b.

https://www.mathworks.com/help/hdlcoder/release-notes.html

You can further use custom latency options to control latency on the block.