HDL System Blockset FPGA design generation Error

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Shady
Shady 2022-8-4
评论： Shady 2022-9-15
I am trying to downsample my data in FPGA using xilinx SoC blockset. I downsampled data using FIR Filters and downsampler and it downsamples correctly as I can see using color legends in simulink and data is also downsampled in simulation but when I tried to compile it using SoC Buiilder it gave me this error "HDL System Blockset FPGA design generation requires all input and output ports use the same sample rate" so I applied some Multirate SoC Design techniques which involved using rate transition blocks. In simulation it shows correct data recieved at processor side but after making the bitfile and running on hardware the data after conversion from u32 to comlpex doesn't make sense like it is neither noisy data nor actual data it is some thing else. i am posting screenshot of my design and data output
Above mentioned is design and below is Actual Output and Simulated Ouput
Kindly help in this regard is this downsampling issue or transition block issue.
Currently I am trying to compile it using HDL Workflow Advisor it is giving me this error

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Chandra Adusumalli
Chandra Adusumalli 2022-8-11
Hi Shady,
Please use proper downsampler for data and use same rate trantition block for valid and ready signals in your design. Then, generate the bit file and try it on hardware.
For hdl workflow adviser error, you need to run the HWA on DUT model only and not on FPGA model. Run the HWA on DUT model itself.
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Shady
Shady 2022-9-15
Thank you for replying. I figured it out by using Upsampler(inserting 0 for N-1 cycles) before sending data into FIFO this way it removed that error of "HDL System Blockset FPGA design generation requires all input and output ports use the same sample rate". But it was using much resources moreover Filter repsonse using Auto Coefficients was not good so I used this example and it helped alot.
Example: Implement Digital Downconverter for FPGA

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