SPI interface timing with deasserts
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I'm looking for a way to read data from a Si8380S-IU chip from a TI F2337xD based processor.
The Simulink examples for Master Transfer are for EEPROM, where the chip select is asserted, the Mode, Address and Data are clocked in and the CS then removed. However the Digital to Analogue chip data sheet requires a CS assert, along with the Mode, then a deassert before the reassert and Register number is clocked in and a final deassert a resassert with the data byte.
There do not appear to be any parameters in the c28x modules that can cause this behaviour. Adding a dozen charts each with a three subsystems to apply the three parameters with an appropriate wait in-between for each chip is untidy and difficult to maintain to say the least.
A pointer to any examples where this has been achieved would be appreciated
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Aditya Pahariya
2023-7-6
Hi ,
You can refer to this example
In the initialization Subsystem, you can see how 'function-call split' has been used to sequence the SPI send and receive.
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2022-10-18
2023-7-6
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