Error when converting design from Matlab Simulink to HDL

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I am a newbie here. I really hope someone can help me with this problem. I made a simple design using simulink and did it convert it to VHDL language however it throws an error: "Slope and bias scaling 'sfix64_S9p765625en13' is not supported for HDL code generation. Slope must be equal to a power of 2, and bias should always be 0". I've been messing around for a week but haven't fixed it yet. I very much hope maybe someone knows how to solve it here. Thank you so much everyone.
This is the file simulink:
  1 个评论
Walter Roberson
Walter Roberson 2023-6-19
How did the sfix64_S9p765625en13 output get chosen?
The error is effectively saying that it is not permitted for VHDL purposes to have a conversion which is (INTERNAL times 9 plus 765625) and that instead you have to use (INTERNAL times 2^some_power + 0) . Or to put it another way, you can only use power-of-2 scaling, EXTERNAL = 2^N * INTERNAL for some integer N.

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回答(1 个)

Kiran Kintali
Kiran Kintali 2023-6-19
The model has an incorrect/undefined type specification. You need to use the fixdt(1,64,32) syntax.
In addition, please note HDL Coder does not currently support Slopbias scaling. Hardware friendly binary point scaling is suitable for HDL Code generation.
  2 个评论
Kiran Kintali
Kiran Kintali 2024-6-28,13:00
编辑:Kiran Kintali 2024-6-28,13:46
>> a = fixdt(1,64,32)
a =
NumericType with properties:
DataTypeMode: 'Fixed-point: binary point scaling'
Signedness: 'Signed'
WordLength: 64
FractionLength: 32
IsAlias: 0
DataScope: 'Auto'
HeaderFile: ''
Description: ''
>> b = numerictype(1,64,32)
b =
DataTypeMode: Fixed-point: binary point scaling
Signedness: Signed
WordLength: 64
FractionLength: 32
>> range(b)
ans =
1.0e+09 *
-2.1475 2.1475
DataTypeMode: Fixed-point: binary point scaling
Signedness: Signed
WordLength: 64
FractionLength: 32
>>

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