Add 'MARK_DEBUG = "TRUE"' to signals in generated HDL

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Kevin Williams
Kevin Williams 2023-6-19
回答： Kiran Kintali 2023-7-16
I need to mark certain signals in a verilog code generation with the attribute MARK_DEBUG = "TRUE",
for example:
(* MARK_DEBUG = "TRUE" *) wire [15:0] snapshot_addr; // uint16
How do I do this?
Many thanks, Kevin

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采纳的回答

Kiran Kintali
Kiran Kintali 2023-7-16
Currently synthesis attribute specification is limited to certain blocks like product block.
This capability is planned for ports, signals, subsystems and more blocks in the near future releases.
Please reach out to tech support for additional requests in this area.

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