Can I control the HDL to/downto designation used for arrays during HDL generation?
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I have ports to my system that are fixdt data types with port dimensions greater than 1 (set to 8 in this case). When HDL Coder generates VHDL, it used the "to" direction for my arrays, but I want it to use "downto". Can I control this?
I saw a related post from 2019 with repsect to boolean datatypes that said it cannot be controlled with boolean types and I didn't know if that response also applied to fixdt types or if the functionality had been changed.
https://www.mathworks.com/matlabcentral/answers/490836-hdl-coder-to-downto-order
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Kiran Kintali
2023-9-8
The control is available starting R2023b release for boolean arrays.
Generate code for Boolean array with MSB-to-LSB convention
You can now generate code for an array of boolean data in most significant bit (MSB) to least significant bit (LSB) convention. For example, a subsystem with boolean input and output data, the generated VHDL code with the DOWNTO convention has this form:
ENTITY Subsystem IS
PORT ( In1 : IN std_logic_vector(4 DOWNTO 0); -- boolean [5]
Out1 : OUT std_logic_vector(4 DOWNTO 0) -- boolean [5] );
END Subsystem;
You can use this functionality for the VHDL®, Verilog®, and System Verilog target languages.
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Kiran Kintali
2023-9-11
Currently it is limited to scalars (integer, fixed-point types in MATLAB) and array of booleans. I will capture this request for the development team.
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