Can you share your sample model and the release of MATLAB you are encountering this error?
Please find the attached model and the generated code snippet for this subsystem.
>> makehdl('test_selector_mlans/Subsystem')
### Working on the model test_selector_mlans
### Generating HDL for test_selector_mlans/Subsystem
### Using the config set for model test_selector_mlans for HDL code generation parameters.
### Running HDL checks on the model 'test_selector_mlans'.
### Begin compilation of the model 'test_selector_mlans'...
### Working on the model 'test_selector_mlans'...
### Working on... GenerateModel
### Begin model generation 'gm_test_selector_mlans'...
### Copying DUT to the generated model....
### Model generation complete.
### Generated model saved at hdlsrc\test_selector_mlans\gm_test_selector_mlans.slx
### Begin VHDL Code Generation for 'test_selector_mlans'.
### Working on test_selector_mlans/Subsystem as hdlsrc\test_selector_mlans\Subsystem.vhd.
### Generating package file hdlsrc\test_selector_mlans\Subsystem_pkg.vhd.
### Code Generation for 'test_selector_mlans' completed.
### Generating HTML files for code generation report at test_selector_mlans_codegen_rpt.html
### Creating HDL Code Generation Check Report Subsystem_report.html
### HDL check for 'test_selector_mlans' complete with 0 errors, 0 warnings, and 0 messages.
### HDL code generation complete.
>>
Generates the following VHDL code
-- -------------------------------------------------------------
--
-- File Name: hdlsrc\test_selector_mlans\Subsystem.vhd
-- Created: 2023-10-08 12:03:20
--
-- Generated by MATLAB 24.1, HDL Coder 24.1, and Simulink 24.1
--
--
-- -------------------------------------------------------------
-- Rate and Clocking Details
-- -------------------------------------------------------------
-- Model base rate: 1
-- Target subsystem base rate: 1
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: Subsystem
-- Source Path: test_selector_mlans/Subsystem
-- Hierarchy Level: 0
-- Model version: 1.1
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.Subsystem_pkg.ALL;
ENTITY Subsystem IS
PORT( In1 : IN std_logic_vector(31 DOWNTO 0); -- sfix32_En30
In2 : IN std_logic_vector(31 DOWNTO 0); -- sfix32_En30
In3 : IN std_logic_vector(31 DOWNTO 0); -- sfix32_En30
In4 : IN std_logic_vector(31 DOWNTO 0); -- sfix32_En30
Out1 : OUT std_logic_vector(31 DOWNTO 0); -- sfix32_En30
Out2 : OUT std_logic_vector(31 DOWNTO 0) -- sfix32_En30
);
END Subsystem;
ARCHITECTURE rtl OF Subsystem IS
-- Signals
SIGNAL Constant4_out1 : std_logic; -- ufix1
SIGNAL Mux_out1_re : vector_of_signed32(0 TO 1); -- sfix32_En30 [2]
SIGNAL Mux_out1_im : vector_of_signed32(0 TO 1); -- sfix32_En30 [2]
SIGNAL Selector_out1_re : signed(31 DOWNTO 0); -- sfix32_En30
SIGNAL Selector_out1_im : signed(31 DOWNTO 0); -- sfix32_En30
BEGIN
Constant4_out1 <= '1';
Mux_out1_re(0) <= signed(In1);
Mux_out1_re(1) <= signed(In3);
Mux_out1_im(0) <= signed(In2);
Mux_out1_im(1) <= signed(In4);
Selector_out1_re <= Mux_out1_re(0) WHEN Constant4_out1 = '0' ELSE
Mux_out1_re(1);
Selector_out1_im <= Mux_out1_im(0) WHEN Constant4_out1 = '0' ELSE
Mux_out1_im(1);
Out1 <= std_logic_vector(Selector_out1_re);
Out2 <= std_logic_vector(Selector_out1_im);
END rtl;
