[Error in dnnfpga.apis.Workflow/compileNetwork] - Enable the Resize2D

Question

Ngo Hieu Truong 2023-10-23

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此问题的直接链接

https://ww2.mathworks.cn/matlabcentral/answers/2037156-error-in-dnnfpga-apis-workflow-compilenetwork-enable-the-resize2d

回答： Wang Chen 2023-10-23

I tried to compile the yolov3 tiny model according to the instructions : https://www.mathworks.com/help/deep-learning-hdl/ug/detect-objects-using-yolov3-network-deployed-to-fpga.html

I changed net to tiny-yolov3-coco and board to Intel - Arria 10 SOC.

When I run command : dn = compile(hW);

result:

Prepending following Altera Quartus II path(s) to the system path:

/home/trolny/intelFPGA/18.1/quartus/bin

Setting QUARTUS_64BIT environment variable to 1 to turn on 64-bit processing.

### Compiling network for Deep Learning FPGA prototyping ...

### Targeting FPGA bitstream arria10soc_single.

### An output layer called 'Output1_conv2d_10' of type 'nnet.cnn.layer.RegressionOutputLayer' has been added to the provided network. This layer performs no operation during prediction and thus does not affect the output of the network.

### An output layer called 'Output2_conv2d_13' of type 'nnet.cnn.layer.RegressionOutputLayer' has been added to the provided network. This layer performs no operation during prediction and thus does not affect the output of the network.

### Optimizing network: Fused 'nnet.cnn.layer.BatchNormalizationLayer' into 'nnet.cnn.layer.Convolution2DLayer'

Error using dnnfpga.compiler.codegenfpga

The bitstream does not have a(n) Resize2D block present in the custom processing module. To fix the problem, enable the Resize2D property of the custom module in the processor configuration and generate the bitstream again.

Error in dnnfpga.apis.Workflow/compileNetwork

Error in dnnfpga.apis.Workflow/compile

How can I fix it?

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Answer 1

Wang Chen 2023-10-23

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此回答的直接链接

https://ww2.mathworks.cn/matlabcentral/answers/2037156-error-in-dnnfpga-apis-workflow-compilenetwork-enable-the-resize2d#answer_1339106

Hi Ngo,

The resize2DLayer inside of the Yolo v3 network is not yet supported by DL HDL Toolbox on Intel boards like Arria 10 SoC board. The Yolo v3 network is supported on Xilinx boards. This limitation is documented at here:

https://www.mathworks.com/help/deep-learning-hdl/ug/supported-networks-layers-boards-and-tools.html#mw_db085aaf-3a49-4b38-aa93-439403805cbd

Alternatively, could you use Yolo v2 network on Intel board?

https://www.mathworks.com/help/deep-learning-hdl/ug/vehicle-detection-using-DAG-network-based-yolov2.html

Thanks,

Wang