Adding Zynq board (xc7z020-2clg400) in 'fpgaBoardManager'.

Question

Charanraj Mohan 2023-10-26

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此问题的直接链接

https://ww2.mathworks.cn/matlabcentral/answers/2039141-adding-zynq-board-xc7z020-2clg400-in-fpgaboardmanager

编辑： Charanraj Mohan 2023-10-26

Hi all,

I've been trying to use the Zynq-7020 (official webpage of the board- https://www.myirtech.com/list.asp?id=708) as FIL (FPGA-in-Loop) in Simulink. This FPGA board is commonly called as 'Z-turn V2- board'. For this I need to have the board in the 'fpgaBoardManager'of MATLAB. Firstly, I have to tell few things that I've done so far and using-

1) I have installed MATLAB R2022b and Vivado 2020.2 (which are compartible by https://ch.mathworks.com/matlabcentral/answers/518421-which-versions-of-xilinx-vivado-are-supported-with-which-release-of-hdl-coder for using HDL coder) though I am not using HDL coder.

2) I can establish both serial and ethernet connection using the Zynq-7020 board I have and I can program the .bit file easily using Vivado. The check of connection of the board with MATLAB via ethernet by typing the command "h = zynq" is positive. I did set-up the system root to the Vivado installation directory using the command "hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath','C:\Xilinx\Vivado\2020.2\bin\vivado.bat')".

3) Since my objective is to use the Zynq-7020 board that I have as FIL in Simulink I tried my luck with 'Zybo Zyna-7000 development board'and 'xilinx Zynq ZC702 evaluation kit', as configuration of both are very close to the board I have. The latter one is very close because my board SoC is '' 'xc7z020-2clg400' and SoC of 'xilinx Zynq ZC702 evaluation kit' is 'xc7z020-1clg484'. I first installed HDL Verifier Support Package for Xilinx FPGA Boards as Add-on and in the setting I must pass three important steps-> a) Generate FPGA programming file, b) Program the FPGA, & c) Perform FPGA-in-the-loop. On trying my luck with the two referred board I could not pass all three steps. Using the settings of 'xilinx Zynq ZC702 evaluation kit' I can pass first two steps.

Thanks for patiently reading so far. Here comes the real problem---

4) After reading in one of the support webpages (https://ch.mathworks.com/matlabcentral/answers/454792-fpga-in-the-loop) I decided to clone the settings of the 'xilinx Zynq ZC702 evaluation kit' and edit all that I have in my actual SoC (xc7z020-2clg400). Below picture has the settings I've. Also, I have enclosed the JTAG inteface settings.

Most of the settings options are very clear to me and I am able to fill them except one, which is the FPGA Input Clock. Unfortunately, the designer (https://www.myirtech.com/) of my board and the xilinx Zynq 7000 SoC (xc7z020-2clg400) did not pull the FPGA's input clock (crystal oscillator's clock) at any external visible pin. So, I can not mentioned the Clock Pin Number. I noticed- mentioning a wrong pin (of course, where clock is allowed on the FPGA's pin) that does not have 33.333333 MHz clock (input frequency of my FPGA board) results in passing first two steps and failing to perform FPGA-in-the-loop. This also leds to error in serial communication window (attached as pic) as 'sii902x 0-003b: i2c bus error!!!', which clearly points SiT902 2.5V LVDS 33.333333 MHz fixed-frequency oscillator (SiTime). In my understanding, the FPGA programming file is loaded and then the FPGA disconnected due to the wrong or missed FPGA input clock.

My question is- if it is possible to override without mentioning the FPGA clock pin and successfully configure to pass all three steps to establish FIL using my Zynq-7020 board (xc7z020-2clg400) ?? Or even in the FPGA-in-the-loop Wizard by directly uploading the VHDL files by mentioning clock signal as 'clk'and reset signal as 'rst' ?? Moreover, in Vivado, in the constraints file (.xdc file) (also attached a picture of it below) of a simple LED blink experiment, we do not mention the pin number of the clock (FPGA output clock) and reset pin as Vivado automatically recognizes my FPGA's output clock when they are labelled as clk and rst.

Any lead to the above mentioned problem is highly appreciated and helpful, as I am really interested to see the Zynq-7020 board working healthier in FIL in the Simulink. Thanks in advance !!!