Setting Target interface fails in Debug Zynq design using HDL and Embedded coder example.
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I am testing out Debug Zynq desing using HDL coder and Embedded coder example but while deploying the model it keeps failing at set target interface. It says some interfaces are not assigned to target interface but I am not sure where these interfaces come from. Please find the Attachment.
Any help will be appreciated.
Thanks in Advance.
-Vishnu
回答（1 个）
Angela Cuadros Castiblanco
2023-11-3
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Hello Vishnu,
The error message you're seeing typically appears when a reference design requires certain non-optional interfaces to be mapped. In other words, these interfaces must be assigned to a port in your design. Based on the interface names in the error message, it seems you might be using the "Receive and Transmit path" reference design, which indeed requires these interfaces to be mapped.
The example you are referencing, Debug Zynq desing using HDL coder and Embedded coder example, uses the "Default System" reference design for the "Xilinx Zynq ZC702 evaluation kit". Could you verify that in task 1.2 "Set Target Reference Design" you set the "Reference design" to "Default System" and in task 1.1 the Target platform is set to "Xilinx Zynq ZC702 evaluation kit"?
Hope that helps!
Angela
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2023-11-3
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