photo

Angela Cuadros Castiblanco

Last seen: Today 自 2023 起处于活动状态

Followers: 0   Following: 0

Spoken Languages:
English, Spanish

统计学

MATLAB Answers

0 个提问
6 个回答

排名
3,098
of 299,793

声誉
18

贡献数
0 个提问
6 个回答

回答接受率
0.00%

收到投票数
3

排名
 of 20,811

声誉
N/A

平均
0.00

贡献数
0 文件

下载次数
0

ALL TIME 下载次数
0

排名

of 166,013

贡献数
0 个问题
0 个答案

评分
0

徽章数量
0

贡献数
0 帖子

贡献数
0 公开的 个频道

平均

贡献数
0 个亮点

平均赞数

  • Knowledgeable Level 2
  • First Answer

查看徽章

Feeds

排序方式:

已回答
How to create this in Simulink? std_logic_vector16 vec[0:3]
Hello Cheri, If you're generating HDL code from a Simulink subsystem using makehdl, the behavior you're describing is already s...

3 months 前 | 1

| 已接受

已回答
Specify clock pins in HDL Reference Design
Hi John, The addClockInterface API in HDL Coder requires you to specify a connection point in your design. For instance, if you...

8 months 前 | 1

| 已接受

已回答
simulink ip core generation
Hello, To use the AXI4-Stream interface in the IP core generation workflow in HDL Coder, you can model your algorithm to operat...

1 year 前 | 0

已回答
AXI-stream interface violates AXI-stream protocol
Hello Alexander, I'd like to provide some clarity on the protocol implementation within our IP core generation workflow. When m...

1 year 前 | 0

已回答
Setting Target interface fails in Debug Zynq design using HDL and Embedded coder example.
Hello Vishnu, The error message you're seeing typically appears when a reference design requires certain non-optional interfac...

2 years 前 | 1

已回答
HDL Workflow Advisor - Step 3.2 - "Failed Index exceeds the number of array elements. Index must not exceed 2" in hdlturnkey.interface.ChannelBased/connectFrameInterfacePort
Hello, From your description it sounds like you are using the "legacy frame-based modeling" detailed in: https://www.mathwor...

2 years 前 | 0

| 已接受