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Angela Cuadros Castiblanco

Last seen: 6 days 前 |  自 2023 起处于活动状态

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simulink ip core generation
Hello, To use the AXI4-Stream interface in the IP core generation workflow in HDL Coder, you can model your algorithm to operat...

3 months 前 | 0

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AXI-stream interface violates AXI-stream protocol
Hello Alexander, I'd like to provide some clarity on the protocol implementation within our IP core generation workflow. When m...

7 months 前 | 0

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Setting Target interface fails in Debug Zynq design using HDL and Embedded coder example.
Hello Vishnu, The error message you're seeing typically appears when a reference design requires certain non-optional interfac...

9 months 前 | 1

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HDL Workflow Advisor - Step 3.2 - "Failed Index exceeds the number of array elements. Index must not exceed 2" in hdlturnkey.interface.ChannelBased/connectFrameInterfacePort
Hello, From your description it sounds like you are using the "legacy frame-based modeling" detailed in: https://www.mathwor...

1 year 前 | 0

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