SystemC code generation directly from SIMULINK model

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I have a SIMULINK model designs that have been compiled as generic ASIC HDL. I would like to convert the design to a SystemC model to start presilicon software development.
The references to SystemC generation that I found so far all assumes starting from MATLAB not Simulink https://www.mathworks.com/help/hdlcoder/systemc-code-generation-from-matlab.html Another question posted asked if SystemC can be generated from HDL Verifier. There was no detail on the process except that SIMULINK coder is required. https://www.mathworks.com/matlabcentral/answers/120830-systemc-code-generation-from-the-hdl-verifier?s_tid=sug_su
I would like to know the steps to generated a SystemC modele from an existing Simulink design that has been successful compiled using HDL Coder.

回答(1 个)

Kiran Kintali
Kiran Kintali 2023-12-24
HDL Coder generates Synthesizable VHDL, Verilog and SystemVerilog for a DUT in Simulink model for targeting ASIC/FPGA/SoC workflows.
Currently Synthesizable SystemC / C++ Code Generation for High Level Synthesis (HLS) workflows is only limited to MATLAB workflows. Simulink support is on the future roadmap. Please reach out to tech support with your usecases for Simulink support.
  4 个评论
John Terry
John Terry 2023-12-27
Kiran
It is not clear to me what the meaing of your comment above.
Are you saying that if you already have a SystemC design that you can use HDL Verifer to have it work with Simulink but the oppose is not true. Meaning, you cannot using HDL Verifier to create SystemC abstraction of the Simulink mode?
If you mean that HDL Verifier cannot be used to generate SystemC abstraction model, then what is the meaning of this text
The TLM generation tool provides a default socket and memory configuration. To customize the socket and memory map of the TLM component, provide an IP-XACT™ file. You can configure the generated component to use a SystemC thread or a callback function.
HDL Verifier generates a TLM test bench, test vectors, and a makefile to verify the component and assist with integration into your HDL simulator environment.

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