You can follow this example to see how to customize the generated DL Processor with HDL Coder.
Customize Bitstream Configuration to Meet Resource Use Requirements
This example shows how to deploy a digit recognition network with a target performance of 500 frames per second (FPS) to a Xilinx™ ZCU102 ZU4CG device. The target device resource counts are:
- Digital signal processor (DSP) slice count — 240
- Block random access memory (BRAM) count — 128
The reference zcu102_int8 bitstream configuration is for a Xilinx ZCU102 ZU9EG device. The default board resource counts are:
- Digital signal processor (DSP) slice count — 2520
- Block random access memory (BRAM) count — 912
The default board resource counts exceed the resource budget and are on the higher end of the cost spectrum. In this example, you can achieve target performance and resource use budget by quantizing the target deep learning network and customizing the bitstream configuration.
