Stateflow while-logic dead loop

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Dingxin Wang 2024-3-28

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https://ww2.mathworks.cn/matlabcentral/answers/2100006-stateflow-while-logic-dead-loop

编辑： Fangjun Jiang 2024-3-29，19:13

I'am using stateflow to model a system.

With this logic i am expecting if the input is 1, the output should be 1. If the input is not 1, do nothing (it'a one-time logic, if the input is once not 1, the output will be none from then).

I used a step signal from 1 to 2 as an input. But the simulation can't proceed since its a dead loop at first time step. Why is that and how to solve this?

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VBBV 2024-3-28

Try using a continuous signal instead of step signal

Dingxin Wang 2024-3-28

yes i tried to use a signal builder to build a continuous signal but it still didnt work

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Answer 1

Fangjun Jiang 2024-3-28

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https://ww2.mathworks.cn/matlabcentral/answers/2100006-stateflow-while-logic-dead-loop#answer_1432976

When input==1, you do have an infinite loop, right?

Connecting the feedback transition to the bottom junction would resolve it.

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Dingxin Wang 2024-3-29，2:09

hi, i dont really understand the infinite loop here. In the loop there is a precondition (input == 1), when the input changes to 2, it should jump out of the loop. How can i understand this?