Cannot write to AXI-Lite registers [HDL coder, PYNQ, HDL Vision toolbox]

Question

Anton Wasser 2024-4-14，12:27

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此问题的直接链接

https://ww2.mathworks.cn/matlabcentral/answers/2106661-cannot-write-to-axi-lite-registers-hdl-coder-pynq-hdl-vision-toolbox

编辑： Kiran Kintali 2024-4-15，20:55

Hello, I am trying to implement a sobel filter using HDL Coder from simulink but I have some issues. For some reason, I am unable to write to the AXI-Lite registers for starting the IP and setting parameters. The target interface for the video stream is AXI-Stream and I am transferring data to it via the DMA IP. I am using PYNQ to control the IP. Below is an example of what is wrong:

As you can see the IP datetime holds the value when I created the IP so I can access that register atleast. However I am unable to set the start and parameter registers, so the IP is unusable. Passing a frame to the IP via DMA only results in a blank frame being returned. I initally suspected the TLAST signal to be the culprit, but according to this document TLAST will be set based on the frame size parameters:

https://se.mathworks.com/help/hdlcoder/ug/model-design-for-axi4-stream-interface-generation.html

Thanks in advance for any answers. I am new to using Matlab/simulink for hdl code generation so sorry if I missed something that should be obvious.

EDIT: I attempted to write the registers with devmem2, and the results were the same except i got bus error for every other register. Which rules out PYNQ incompatibility, but confuses me

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Answer 1

Kiran Kintali 2024-4-15，20:54

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https://ww2.mathworks.cn/matlabcentral/answers/2106661-cannot-write-to-axi-lite-registers-hdl-coder-pynq-hdl-vision-toolbox#answer_1441716

编辑：Kiran Kintali 2024-4-15，20:55

For sobel filter examples using HDL Coder from Simulink consider reviewing these examples.

(sampleIn and sampleOut DUT)

https://www.mathworks.com/help/hdlcoder/ug/getting-started-with-axi4-stream-video-interface-in-zynq-workflow.html

(frameIn and frameOut DUT)

https://www.mathworks.com/help/hdlcoder/ug/deploy-a-frame-based-model-with-AXI4-Stream-interfaces.html

You can also see how interact with the FPGA in the seciton "Live Frame-Based Model Running on FPGA" in the above example. There are examples in there on how to read and write a Frame in MATLAB.

I am assuming you have your own PYNQ setup where you are interacting with HDL Coder generated IP Core. If this is the case you might want to review the section which talks about AXI4RegisterReadback for AXI lite registers

https://www.mathworks.com/help/hdlcoder/ug/model-design-for-axi4-slave-interface-generation.html

hdlset_param('hdlcoder_led_vector/DUT', 'AXI4RegisterReadback', 'on');

If you want additional control on DUT IP ports that you model at Simulink DUT level there is additional guidance here... https://www.mathworks.com/help/hdlcoder/ug/readback-AXI4-input-register.html

Feel free to share your model and setup for additional support.