How to give random inputs for my simulink design?

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Utkarsh
Utkarsh 2024-4-16
回答： Kiran Kintali 2024-4-21
I have created a model using importhdl ie. from my verilog code. Now I want to test it with many random inputs just like we do simulation testing on iVerilog or Quartus Prime or any other HDL tool. How can I do that as if I use constant then it works for only one input at a time?

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Kiran Kintali
Kiran Kintali 2024-4-21
You have to wrap the imported Simulink model from HDL Code into a subsystem. Add sources (constants, toworkspace blocks...) and sinks (displays, scopes, ...) and drive the design.
The importhdl command currently only tries to import a synthesizable HDL design (limitations exist) into a subset of supported Simulink constructs. Only Verilog import is supported as of R2024a release and VHDL support is on the roadmap.
Currently importhdl cannot automatically import a testbench for your DUT.

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