Hi Shalini,
Try following these steps for troubleshooting:
1. Check Hardware Connectivity:
- I hope you referred to the documentation https://www.mathworks.com/help/hdlverifier/ug/troubleshooting-fil.html.
- Verify all power and network cables are functional.
- Create a static entry in the ARP cache.
- Consider changing your HDL design frequency to 25MHz and rebuild.
2. Network Connectivity:
- Ensure a dedicated point-to-point connection between your host and the FPGA board:
- Use separate NICs on your computer for intranet and FPGA communication.
- Connect the FPGA directly to your machine, avoiding hubs.
- Set a compatible IP address and subnet mask on your PC (e.g., 192.168.0.1 for crossover connection).
3. Firewall and File Access:
- Disable firewalls or open appropriate ports to allow communication between the board and host.
- Verify your HDL design resides on a local or mapped drive (not a UNC path).
4. Cleaning Up and Restarting:
- Delete the generated "fil_test" folder and any other auto-generated folders.
- Restart the validation process in a clean folder.
5. Advanced Troubleshooting (if previous steps fail):
- Install Wireshark and capture network activity:
- Capture ping logs to the board's IP address (e.g., 192.168.0.2) during validation.
- Send these logs (along with a workflow description) to MathWorks support (support@mathworks.com).
- Analyze the command window output during bitstream generation for successful generation and timing violations.
- Send the command window contents (along with a workflow description) to MathWorks support.
By following these steps systematically, you should be able to identify the cause of the FIL validation error and resolve the issue. If you continue to face problems, contacting MathWorks support with the requested information will provide further assistance.
