See the attached sample code that demonstorates (line 15, 16) on how create large arrays.
I am assuming you are using MATLAB to HDL and not MATLAB function block in Simulink. If it is MATLAB to HDL workflow you can follow the steps below. If it is Simulink to HDL you need to plug in the above function into a MATLAB function block and run HDL Codegeneration steps.
For MATLAB to HDL here are the compilation steps.
fixptCfg = coder.config('fixpt');
fixptCfg.TestBenchName = 'mlhdlc_heq_24a_tb';
cfg = coder.config('hdl');
cfg.TestBenchName = 'mlhdlc_heq_24a_tb';
codegen -float2fixed fixptCfg -config cfg mlhdlc_heq_24a -launchreport
The above command runs fixed-point conversion (optionally) and HDL Code generation
===================================================
Design Name: mlhdlc_heq_24a
Test Bench Name: mlhdlc_heq_24a_tb
===================================================
Input types not specified for design(s) 'mlhdlc_heq_24a', inferring types by simulating the first test bench: 'mlhdlc_heq_24a_tb' in the base workspace.
============= Step1: Analyze floating-point code ==============
Code generation successful.
============= Step1a: Verify Floating Point ==============
### Analyzing the design 'mlhdlc_heq_24a'
### Analyzing the test bench(es) 'mlhdlc_heq_24a_tb'
### Begin Floating Point Simulation (Instrumented)
working on frame: 1
working on frame: 2
### Floating Point Simulation Completed in 3.4729 sec(s)
### Elapsed Time: 4.2094 sec(s)
============= Step2: Propose Types based on Range Information ==============
============= Step3: Generate Fixed Point Code ==============
### Generating Fixed Point MATLAB Code mlhdlc_heq_24a_fixpt using Proposed Types
### Generating Fixed Point MATLAB Design Wrapper mlhdlc_heq_24a_wrapper_fixpt
### Generating Mex file for ' mlhdlc_heq_24a_wrapper_fixpt '
Code generation successful: View report
### Generating Type Proposal Report for 'mlhdlc_heq_24a' mlhdlc_heq_24a_report.html
===================================================
Code generation successful.
### The DUT requires an initial pipeline setup latency. Each output port experiences these additional delays.
### Output port 1: 2 cycles.
### Output port 2: 2 cycles.
### Output port 3: 2 cycles.
### MESSAGE: The design requires 2 times faster clock with respect to the base rate = 1.
### Working on mlhdlc_heq_24a_fixpt_tc as mlhdlc_heq_24a_fixpt_tc.vhd.
### Begin VHDL Code Generation
### Working on mlhdlc_heq_24a_fixpt/SimpleDualPortRAM_generic as SimpleDualPortRAM_generic.vhd.
### Working on mlhdlc_heq_24a_fixpt_enb_bypass as mlhdlc_heq_24a_fixpt_enb_bypass.vhd.
### Working on mlhdlc_heq_24a_fixpt as mlhdlc_heq_24a_fixpt.vhd.
### Generating package file mlhdlc_heq_24a_fixpt_pkg.vhd.
### Generating Resource Utilization Report resource_report.html.
### Generating HDL Conformance Report mlhdlc_heq_24a_fixpt_hdl_conformance_report.html.
### HDL Conformance check complete with 0 errors, 0 warnings, and 1 messages.
### Code generation successful: View report
