Not able to Build FPGA BitStream for Simscape example model Half Wave Rectifier

Question

Avani 2024-4-29

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https://ww2.mathworks.cn/matlabcentral/answers/2112976-not-able-to-build-fpga-bitstream-for-simscape-example-model-half-wave-rectifier

评论： Kiran Kintali 2024-5-1

Hello Everyone ,

I am referring to link : https://www.mathworks.com/help/hdlcoder/ug/simscape-hil-speedgoat-fpga-io-modules.html,

in which when trying to generate FPGA bitstream for 'gmStateSpaceHDL_sschdlexHalfWaveRectifierEx/Simscape_system/HDL Subsystem' , the simulink doesnot proceed from Section 4.2 , I have waited for around 3hrs and followed all steps mentioned in above link

Kindly help me resolve the issue

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Answer 1

Kiran Kintali 2024-4-29

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https://ww2.mathworks.cn/matlabcentral/answers/2112976-not-able-to-build-fpga-bitstream-for-simscape-example-model-half-wave-rectifier#answer_1449701

https://www.mathworks.com/help/hdlcoder/ug/simscape-hil-speedgoat-fpga-io-modules.html

What version of synthesis tools AMD/Xilinx Vivado are you using currently?

The demo should work as expected in 23a. Have you also tried using 24a? Is it the same behavior? The screenshot shows you are stuck in Vivado bitstream step; it may unlikely be an issue on the HDL Coder side.

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Answer 2

Avani 2024-5-1

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https://ww2.mathworks.cn/matlabcentral/answers/2112976-not-able-to-build-fpga-bitstream-for-simscape-example-model-half-wave-rectifier#answer_1450676

As i am using 23a, vivado version applicable is 2022.1 , but if I use Vivado 2020.2, does it has any impact while generating Bitstream. Because previously I was able to generate few bitstreams using this same procedure and same versions