fixing clock frequency and sample time of control system model using hdl coder

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Gary
Gary 2024-6-19
编辑： Kiran Kintali 2024-6-20
I have built a fixed point PID controller in simulink and could generate the code using hdl coder for programming FPGA. The generated verilog code has additional inputs such as clock, clock enable. During simulation, I fixed the sample time of the discrete models to .01 seconds. I am unable to understand the difference between the input clock and the sample time. Could you please clarify? (btw My FPGA recieves external clock of 50MHz)

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Kiran Kintali
Kiran Kintali 2024-6-20
编辑：Kiran Kintali 2024-6-20

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